Altera推荐的 Verilog HDL Clock Multiplexing Design to Avoid Glitches
module clock_mux (clk,clk_select,clk_out);parameter num_clocks = 4;
input clk;
input clk_select; // one hot
output clk_out;
genvar i;
reg ena_r0;
reg ena_r1;
reg ena_r2;
wire qualified_sel;
// A look-up-table (LUT) can glitch when multiple inputs
// change simultaneously. Use the keep attribute to
// insert a hard logic cell buffer and prevent
// the unrelated clocks from appearing on the same LUT.
wire gated_clks /* synthesis keep */;
initial begin
ena_r0 = 0;
ena_r1 = 0;
ena_r2 = 0;
end
generate
for (i=0; i<num_clocks; i=i+1)
begin : lp0
wire tmp_mask;
assign tmp_mask = {num_clocks{1'b1}} ^ (1 << i);
assign qualified_sel = clk_select & (~|(ena_r2 & tmp_mask));
always @(posedge clk) begin
ena_r0 <= qualified_sel;
ena_r1 <= ena_r0;
end
always @(negedge clk) begin
ena_r2 <= ena_r1;
end
assign gated_clks = clk & ena_r2;
end
endgenerate
// These will not exhibit simultaneous toggle by construction
assign clk_out = |gated_clks;
endmodule 循环设计避免毛刺 Altera推荐的 Verilog HDL Clock Multiplexing Design to Avoid Glitches Altera推荐的 Verilog HDL Clock Multiplexing Design to Avoid Glitches endgenerate 不错，谢谢分享~~~~~~~~~~
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