tlc5620的时序问题，各位看看问题出在哪里
module tlc5620 (input clk_50MHz,
input rst_n,
output da_clk,
output da_load,
output da_ldac,
output da_data
);
wire clk_1MHz;
reg data;
reg num;
always @(posedge clk_1MHz or negedge rst_n)
begin
if(!rst_n)
begin
num<=4'd0;
data<=8'd100;
end
else
begin
if(num==12)
begin
num<=4'd0;
end
else
begin
num<=num+1'd1;
end
end
end
reg da_data_r;
always @(posedge clk_50MHz or negedge rst_n)
begin
if(!rst_n)
begin
da_data_r<=1'b0;
end
else
begin
case(num)
4'd0:da_data_r<=1'b0;
4'd1:da_data_r<=1'b0;
4'd2:da_data_r<=1'b0;
4'd3:da_data_r<=data;
4'd4:da_data_r<=data;
4'd5:da_data_r<=data;
4'd6:da_data_r<=data;
4'd7:da_data_r<=data;
4'd8:da_data_r<=data;
4'd9:da_data_r<=data;
4'd10:da_data_r<=data;
4'd11:da_data_r<=1'b0;
4'd12:da_data_r<=1'b0;
default:;
endcase
end
end
assign da_data=da_data_r;
assign da_clk=clk_1MHz;
assign da_load=(num==11)?1'b0:1'b1;
assign da_ldac=(num==12)?1'b0:1'b1;
pll pll_dut (
.areset(rst_n),
.inclk0(clk_50MHz),
.c0(clk_1MHz)
);
endmodule 你可以讲仿真波形，放在这里看看，这样更容易找问题
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