求助一下关于串口发送32位数据的问题
下面是我用Verilog写的发送8位数据的uart通信，key1是开发板上按键，按下则把设定好的8位数据发给上位机。但是我现在需要传送32位数据，应该是把32位分为4组，一组8个依次发送，但是我是新手，不知道怎么加状态判断，让 tx_data1的4组依次发送，哪位大神帮我修改一下我的程序，或者给我详细讲解一下，让它可以传送32位数据。module uart (
input clk
input key1,
input rst_n,
output reg txd
);
parameter S1_IDLE=4'd0;
parameter S1_START=4'd1;
parameter S1_BIT0=4'd2;
parameter S1_BIT1=4'd3;
parameter S1_BIT2=4'd4;
parameter S1_BIT3=4'd5;
parameter S1_BIT4=4'd6;
parameter S1_BIT5=4'd7;
parameter S1_BIT6=4'd8;
parameter S1_BIT7=4'd9;
parameter S1_STOP=4'd10;
wire tx_data1;
assign tx_data1=8'h5c;
reg state;
reg bit_timer;
always @ (posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
state<=S1_IDLE;
bit_timer<=16'd0;
txd<=1'b1;
end
else
begin
case (state)
S1_IDLE:
begin
bit_timer<=16'd0;
txd<=1'b1;
if(!key1)
state<=S1_START;
else
state<=state;
end
S1_START:
begin
txd<=1'b0;
if(bit_timer==16'd20833)
begin
state<=S1_BIT0;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT0:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT1;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT1:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT2;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT2:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT3;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT3:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT4;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT4:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT5;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT5:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT6;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT6:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_BIT7;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_BIT7:
begin
txd<=tx_data1;
if(bit_timer==16'd20833)
begin
state<=S1_STOP;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
S1_STOP:
begin
txd<=1'b1;
if(bit_timer==16'd20833)
begin
state<=S1_IDLE;
bit_timer<=16'd0;
end
else
begin
state<=state;
bit_timer<=bit_timer+16'd1;
end
end
default:
begin
state<=S1_IDLE;
end
endcase
end
end
endmodule
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