SDRAM页读状态机设计程序——仅供参考
/*------------------------------------??????? ?? SDRAM?????
?????? ?????��???????????1????????????��?��????bank???
2??????tRCD???????????��?????��?????????a?????????
3?????????????????????????
--2015-10-08
-------------------------------------*/
`include "sdram_head.v"
module sdr_read(capture_clk, sys_clk, rd_rst_n, int_addr, rd_data, rd_done, rd_bus, sdr_dq, valid);
input sys_clk;
input capture_clk;
input rd_rst_n;
input int_addr;
input sdr_dq;
output reg rd_done;
output reg rd_data;
output reg rd_bus;
output reg valid;
localparam s0 = 3'b000;
localparam s1 = 3'b001;
localparam s2 = 3'b010;
localparam s3 = 3'b011;
localparam s4 = 3'b100;
localparam s5 = 3'b101;
reg state;
reg count;
// reg load_h;
// reg load_l;
reg cap_dq;
reg sys_dq;
reg sys_dq_int;
always @ (posedge capture_clk)
begin : capture_reg
if (!rd_rst_n)
cap_dq <= 16'd0;
else
cap_dq <= sdr_dq;
end
always @ (posedge sys_clk)
begin : sync_reg
if (!rd_rst_n)
begin
sys_dq <= 16'd0;
sys_dq_int <= 16'd0;
end
else
begin
sys_dq_int <= cap_dq;
sys_dq <= sys_dq_int;
end
end
always @ (posedge sys_clk)
begin : read_fsm_1s
if (!rd_rst_n)
begin
rd_bus <= `NOP;
rd_bus <= 1;
rd_bus <= 0;
count <= 0;
rd_done <=0;
state <= s0;
rd_data <= 0;
valid <= 0;
end
else
case (state)
s0 : begin
rd_bus <= `ACT;//???????????
rd_bus <= 1;
rd_bus <= int_addr; //????bank???
rd_bus <= int_addr;//?????��??
state <= s1;
end
s1 :if (count < `tRCD-1)
begin
rd_bus <= `NOP;
count <= count + 1'b1;
end
else
begin
rd_bus <= `RD;
rd_bus <= int_addr;//Bank???
rd_bus <= 1; //a10=1?????????????????????????????????
rd_bus <= int_addr; //?��??
count <= 0;
state <= s2;
end
s2 : if (count < 3)
begin
rd_bus <= `NOP;
count <= count + 1'b1;
end
else
begin
count <= 0;
state <= s3;
end
s3 : if (count == 0)
begin
valid <= 1;
rd_data <= sys_dq;
count <= count + 1'b1;
end
else if (count > 0 && count < `RD_SIZE)
begin
valid <= 1;
rd_data <= sys_dq;
count <= count + 1'b1;
end
else
begin
rd_bus <= `BT; //????????????????????????
count <= 0;
valid <= 1;
rd_data <= sys_dq;
state <= s4;
end
// s3 : if (count < `RD_SIZE)
// begin
// valid <= 1;
// rd_data <= sys_dq;
// count <= count + 1;
// end
// else
// begin
// rd_bus <= `BT; //????????????????????????
// count <= 0;
// valid <= 1;
// rd_data <= sys_dq;
// state <= s4;
// end
s4 : begin ////???????????????5????��??????4
if (count < `RD_DATA_LY)//????3?????????sdram??????????�o?????????????
begin
count <= count + 1'b1;
valid <= 1;
rd_data <= sys_dq;
rd_bus <= `NOP;
end
else
begin
count <= 0;
valid <= 0;
rd_bus <= `PRECHANGE;
state <= s5;
end
end
s5 : begin
rd_bus <= `NOP;
rd_data <= 0;
rd_done <= 1;
end
default : rd_bus <= `NOP;
endcase
end
endmodule SDRAM页读状态机设计程序——仅供参考
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