SDRAM页写状态机设计程序——仅供参考
/*--------------------------------------------模块名称 ： SDRAM写模块
模块说明 : 当有写事件发生时：1.发送激活命令、行地址、bank地址
2.经过tRCD之后，发送写命令、列地址、写数据、a拉高标志自动刷新
3.继续发送第二个数据（BL=2）
--2015-10-08
--------------------------------------------*/
module sdr_write(wr_rst_n, sys_clk, int_addr, wr_done, wr_bus, int_dq, out_en, local_wdata, wr_data_ok);
input sys_clk;
input wr_rst_n;
input int_addr;
input local_wdata;
output reg wr_done;
output reg wr_bus;
output reg int_dq;
output reg out_en;
output reg wr_data_ok;
localparam s0 = 3'b000;
localparam s1 = 3'b001;
localparam s2 = 3'b010;
localparam s3 = 3'b011;
localparam s4 = 3'b100;
localparam s5 = 3'b101;
reg state;
reg count;
always @ (posedge sys_clk)
begin
if (!wr_rst_n)
begin
wr_bus <= `NOP;
wr_bus <= 1;
wr_bus <= 0;
int_dq <= 0;
count <= 0;
out_en <= 0;
wr_done <=0;
state <= s0;
wr_data_ok <= 0;
end
else
case (state)
s0 : begin
wr_bus <= `ACT; //发送激活命令
wr_bus <= int_addr; //发送bank地址
wr_bus <= int_addr;//发送行地址
state <= s1;
wr_data_ok <= 1;
end
s1 :if (count < `tRCD-1)//`tRCD-1 = 1
begin
wr_bus <= `NOP;
count <= count + 1'b1;
end
else
begin
wr_bus <= `WR;
wr_bus <= int_addr;
wr_bus <= 1; //拉高a,自动刷新
wr_bus <= int_addr; //列地址
int_dq <= local_wdata;
out_en <= 1;
count <= 0;
state <= s2;
end
s2 : begin
if (count < `WR_SIZE)
begin
int_dq <= local_wdata;
out_en <= 1;
count <= count + 1'b1;
wr_bus <= `NOP;
end
else if(count == `WR_SIZE)
begin
int_dq <= local_wdata;
out_en <= 1;
count <= count + 1'b1;
wr_data_ok <= 0;
end
else
begin
int_dq <= local_wdata;
out_en <= 1;
count <= 0;
state <= s3;
end
end
s3 : begin
out_en <= 0;
wr_bus <= `BT;//发出突发终止命令
state <= s4;
end
s4 : begin
if (count < 2)
begin
count <= count + 1'b1;
wr_bus <= `NOP;
end
else
begin
count <= 0;
wr_bus <= `PRECHANGE;
wr_bus <= 1;
state <= s5;
end
end
s5 :if (count < 2)
begin
count <= count + 1'b1;
wr_bus <= `NOP;
end
else
begin
wr_done <= 1;
end
default : wr_bus <= `NOP;
endcase
end
endmodule SDRAM页写状态机设计程序——仅供参考
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