iis_capture
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity iis_capture is
port(
reset :in std_logic;
--iis interface
lrclk :in std_logic;
sclk :in std_logic;
sdi :in std_logic;
--iis data
data :out std_logic_vector(31 downto 0);
data_rdy :out std_logic;
test_point :out std_logic
);
end iis_capture;
architecture arch_iis_capture of iis_capture is
signal lr_flag, lr_flag_temp : std_logic;
signal iis_capture_permit : std_logic:='0';
signal counter : integer range 63 downto 0;
signal l_ch_valid, r_ch_valid : std_logic;
signal data_num : integer range 31 downto 0;
signal data_test : std_logic_vector(31 downto 0);
begin
process(sclk, reset)
begin
if reset='1' then
lr_flag <= '0';
lr_flag_temp <= '0';
elsif sclk'event and sclk='1' then
lr_flag <= lrclk;
lr_flag_temp <= lr_flag;
end if;
end process;
iis_capture_permit <= '1' when lr_flag='0' and lr_flag_temp='1';
process(sclk, reset, iis_capture_permit)
begin
if reset='1' then
counter <= 0;
elsif (sclk'event and sclk='1') and iis_capture_permit='1' then
if counter = 63 then -- 64 sclk per cycle
counter <= 0; -- counter is 0 at 64th sclk rising edge
else
counter <= counter + 1;
end if;
end if;
end process;
l_ch_valid <= '1' when counter>=0 and counter<=15 else
'0';
r_ch_valid <= '1' when counter>=32 and counter<=47 else
'0';
process(sclk, reset, iis_capture_permit)
begin
if reset='1' then
data <= X"0000_0000";
elsif (sclk'event and sclk='1') and iis_capture_permit='1' then
if l_ch_valid='1' or r_ch_valid='1' then
data(data_num) <= sdi;
data_test(data_num) <= sdi;
end if;
end if;
end process;
data_num <= 31 - counter when l_ch_valid='1' else
47 - counter when r_ch_valid='1' else
0;
data_rdy <= '1' when counter=48 else
'0';
test_point <= iis_capture_permit;
end arch_iis_capture;
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