sale.v
module sale(
input clk,
input rst_n,
input momy,//01琛ㄧず5鍒嗭紝10琛ㄧず10鍒?
output reg yl,//yl=1琛ㄧず杈撳嚭楗枡
output reg zl//zl=1琛ㄧず鎵鹃浂
);
parameter IDLE =3'd0,
FEN51 =3'd1,
FEN52 =3'd2,
FEN10= =3'd3;
reg state;
always @(posedge clk or negedge rst_n)
if(~rst_n)
state<=IDLE;
else case(state)
IDLE :if(momy==01)state<=FEN51;
else if(momy==10)state<=FEN52;
FEN51 :if(momy==01)state<=FEN52;
else if(momy==10)state<=FEN10;
FEN52 :state<=IDLE;
FEN10 :state<=IDLE;
endcase
always @(posedge clk or negedge rst_n)
if(~rst_n)begin
zl<=0;
yl <-0;end
else begin
if( (state=FEN52)|| (state==FEN10) )
yl <=1;
else
yl <=0;
if(state==FEN10)
zl<=1'b1;
else
zl<=1'b0;
end
endmodule
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