ISE怎么样优化才能减少Number of Slices的使用率
本帖最后由 fpgaw 于 2010-11-19 17:57 编辑ISE怎么样优化才能减少Number of Slices的使用率 Options Mark as New
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06-06-2008 02:43 PM
Slices are the basic building block components in the FPGA fabric.However each slice contains a number of LUT's, flip-flops, and carry logic elements which make up the logic of your design before mapping.After mapping, all of the LUT's and flip-flops are packed into slices, but not necessarily filling the slices.i.e. a slice with two LUT's and two flip-flops may be in use for just one LUT.In the map report any slice that is used even partially is counted in the "occupied slices".You will usually notice that the percentage of usage of slices is greater than the larger of LUT's and flip-flops.i.e. your design may use about 25% of LUT's and flip-flops but because of sparse packing it can have nearly 50% occupied slices.It may be possible to fit the design into fewer slices, but if it wasn't necessary (i.e. there are still slices left over) the mapper will not try to pack the logic any further.
When you are struggling to meet timing in a fairly full design, the number of occupied slices is a good indicator of when the mapper will need to start packing unrelated logic into a slice and thus limit the ability of the placer to find a placement that meets timing.This usually happens when occupied slices reach about 95% of the device total.While at this point you may have nearly 50% of the device resources (in LUT's and flip-flops) free, your ability to use the additional resources may be limited by your ability to meet timing constraints after routing delays.If you don't want to delve too deeply into the methods of optimising your design to meet timing, it is generally best to keep the filled slices below this level.
regards, occupied slices
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