一个简单的总线轮询仲裁器Verilog实现
// Verilog Module demo1_lib.bus_arbitor.arch_name//
// Created:
// by - Newhand
// in - Shanghai ZhangJiang
// at - 20:39:41 2003-12-03
// using Mentor Graphics HDL Designer(TM)
//
///////////////////////////////////////////////////////////
// Discription:
// Bus Polling Arbitor (BPA)
// 总线上挂3个信号A,B,C，仲裁信号grant。
// grant=2’b00 A获得总线
// grant=2’b01 B获得总线
// grant=2’b10 C获得总线
// 总线轮询算法a.如果当前只有一个信号请求，则处理.
// b.如果没有请求，那么A获得总线.
// c.如果同时有多个信号请求，考虑上一个请求信号，
// 如果上一个请求信号是A，那么轮询的是BCA，
// 如果上一个请求信号是B，那么轮询的是CAB，
// 如果上一个请求信号是C，那么轮询的是ABC
//////////////////////////////////////////////////////////
`resetall
`timescale 1ns/10ps
module bus_arbitor(clk_i, en_i, sig_a_i, sig_b_i, sig_c_i, grant_o);
// I/O definition
input clk_i;
input en_i;
input sig_a_i;
input sig_b_i;
input sig_c_i;
output grant_o;
// register definition
reg grant_o;
reg ls;
// parameter definition
parameter s_null = 'd0,
s_a = 'd1,
s_b = 'd2,
s_c = 'd3,
s_ab = 'd4,
s_bc = 'd5,
s_ac = 'd6,
s_abc= 'd7;
//module part and FSM
always @(posedge clk_i or negedge en_i)
if(!en_i)// bus disable when negtive en_i
begin
grant_o <= 2'b11;
//cs <= s_null;
ls <= s_null;
end
else
begin
case({sig_a_i, sig_b_i, sig_c_i})// bus enable with FSM
s_null:
begin
grant_o <= 2'b00;
ls <= s_a;
end
s_a:
begin
grant_o <= 2'b00;
ls <= s_a;
end
s_b:
begin
grant_o <= 2'b01;
ls <= s_b;
end
s_c:
begin
grant_o <= 2'b10;
ls <= s_c;
end
s_ab:
case(ls)// feedback MUX configured
s_a: begin grant_o <= 2'b01; ls <= s_b; end
s_b: begin grant_o <= 2'b00; ls <= s_a; end
s_c: begin grant_o <= 2'b00; ls <= s_a; end
endcase
s_bc:
case(ls)
s_a: begin grant_o <= 2'b01; ls <= s_b; end
s_b: begin grant_o <= 2'b10; ls <= s_c; end
s_c: begin grant_o <= 2'b01; ls <= s_b; end
endcase
s_ac:
case(ls)
s_a: begin grant_o <= 2'b10; ls <= s_c; end
s_b: begin grant_o <= 2'b10; ls <= s_c; end
s_c: begin grant_o <= 2'b00; ls <= s_a; end
endcase
s_abc:
case(ls)
s_a: begin grant_o <= 2'b01; ls <= s_b; end
s_b: begin grant_o <= 2'b10; ls <= s_c; end
s_c: begin grant_o <= 2'b00; ls <= s_a; end
endcase
default:
begin grant_o <= 2'b00; ls <= s_a; end
endcase
end
endmodule :)
谢谢楼主分享，好东西哦！
谢谢楼主分享，好东西哦！
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