小弟：ISE调用modelsim进行前仿真的遇到的麻烦
本帖最后由 fpgaw 于 2010-10-29 12:43 编辑ISE调用modelsim进行前仿真时的出现以前错误，代码中调用了FIFO的IP核。期待高手解答，不胜感激
# Loading work.tt
# Loading work.test_FIFO
# Loading work.test_FIFO_IP
# ** Error: (vsim-3033) ../scr/test_FIFO_IP.v(157): Instantiation of 'FIFO_GENERATOR_V4_4' failed. The design unit was not found.
# Region: /tt/uut/test_FIFO_IP
# Searched libraries:
# C:\Modeltech_xe_starter\xilinx\verilog\xilinxcorelib_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unisims_ver
# C:\Modeltech_xe_starter\xilinx\verilog\unimacro_ver
# E:\test_FIFO_IP_1\test\work
# Loading work.glbl
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./tt.fdo PAUSED at line 9 在simulation时vsim work.(name)_tb.vwork.glbl.v
两个一起仿真
在simulation时vsim work.(name)_tb.vwork.glbl.v
两个一起仿真
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