Error (10278): Verilog HDL Port Declaration error at DEC_top.v(7): input port "IN" cannot be declared with type "<a variable data type, e.g. reg>" 可是加上 reg【3:0】IN， 语法检查就通不过，
Error (10278): Verilog HDL Port Declaration error at DEC ...
CPLD 发表于 2010-5-14 12:30 http://www.fpgaw.com/images/common/back.gif
你在tb里面写
的例化 最好.xx() 改成这样也不对
module DEC_top(IN, OUT, ERR);
input IN;
output OUT;
output ERR;
BCD_decoder DEC_1 (IN, OUT, ERR);
initial begin
IN=0;
for (i=0;i<15;i=i+1)
#50 IN=IN+1;
$finish;
end
endmodule
IN=0; 和 IN=IN+1;这两句出错
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