用VHDL代码产生标准m序列的问题
请教高手，小弟刚学写FPGA代码，最近要做一个低速率的误码仪，要求能与老外的误码仪互换（RAD 公司的LBT误码仪），LBT误码仪说明书上说能与满足ITU V.52标准（该标准已经被ITU O.150替代）的设备兼容，我需要在FPGA里面产生和LBT误码仪相同的m序列，长度是511.------------------------------------这个是ITU标准上说的-----------------------------------
4.1 511-bit pseudo-random test pattern
This pattern is primarily intended for error measurements on data circuits at bit rates up to 14 400 bit/s (see
Recommendation O.153).
The pattern may be generated in a nine-stage shift register whose 5th and 9th stage outputs are added in a
modulo-two addition stage, and the result is fed back to the input of the first stage. The pattern begins with the first ONE
of 9 consecutive ONEs.
Number of shift register stages 9
Length of pseudo-random sequence 2*9-1= 511 bits （2的9次方减1）
Longest sequence of ZEROs 8 (non-inverted signal)
--------------------------------------------------------------------------------------------
按照上面的标准，我理解的该m序列的本原多项式X*9+X*5+1(X的9次方+X的5次方+1)，
---------------------------------我用VHDL写的代码的一个片段---------------------------------------
.....
signal m_code_out : std_logic;
signal fdbk : std_logic;
signal shift_out: std_logic_vector(8 downto 0);
.....
process(clk)
begin
if rising_edge(clk) then
if (reset = '0') then
shift_out <= (others => '1');------初始状态全1
fdbk <= shift_out(8) xor shift_out(4);
else
m_code_out <= shift_out(8);-----最高位移位输出-----（这是我想要的n=9，长度为511的m序列）
shift_out(8 downto 1) <= shift_out(7 downto 0);
fdbk <= shift_out(8) xor shift_out(4);-----第5位和第9位模2加
shift_out(0) <= fdbk;-----第5位和第9位模2加的值作为新的输入
end if;
end if;
end process; 这个问题我已经搞定了，
把 fdbk <= shift_out(8) xor shift_out(4);这句放在process外面就可以呢 把 fdbk <= shift_out(8) xor shift_out(4);这句放在process外面就可以呢
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