论坛 › FPGA技术交流 › 请教Verilog语言中的一个问题

AAT 发表于 2010-6-26 11:54:24

还有就是既然是10010的检测，那么是不是应该100101001010010这样才算3个有效的序列？还是10010010010这样才算？<br>
<br>
个人认为应该是第1种情况才是巴，请高手解答？？？

HDL 发表于 2010-6-26 13:07:35

怎么这么复杂，一个异或补救解决了，flag = state^10010;

longtime 发表于 2010-6-26 14:56:34

谢谢，我刚好也碰到这个问题

AAT 发表于 2010-6-26 16:17:58

夏老师书上的............

ICE 发表于 2010-6-26 16:36:08

我按夏老师书上的测试文件<br>
`timescale 1ns/1ns<br>
module test(x, z, clk, rst);<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg clk,rst;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg data;<br>
&nbsp; &nbsp; &nbsp; &nbsp; wire z,x;<br>
&nbsp; &nbsp;assign x=data;<br>
&nbsp; &nbsp; &nbsp; &nbsp; <br>
&nbsp; &nbsp; &nbsp; &nbsp; initial<br>
&nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp; clk=0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; rst=1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; #2 rst=0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; #30 rst=1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp; data=20'b1100_1001_0000_1001_0100;<br>
&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp;&nbsp;end<br>
&nbsp; &nbsp; &nbsp; &nbsp;&nbsp;&nbsp;always #10 clk=~clk;<br>
&nbsp; &nbsp; &nbsp; &nbsp;&nbsp;&nbsp;always @ (posedge clk)<br>
&nbsp; &nbsp; &nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; data={data,data};<br>
&nbsp; &nbsp; seqdet m(.x(x),.z(z),.clk(clk),.rst(rst));<br>
<br>
<br>
endmodule<br>
综合有问题

encounter 发表于 2010-6-26 17:14:55

好好好,精神可加

CHAN 发表于 2010-6-26 18:09:38

BUCUO BUCUO

interig 发表于 2010-6-26 18:48:47

的确学到不少！

FFT 发表于 2010-6-26 19:38:13

看了有收获

Sunlife 发表于 2015-6-25 10:35:31

楼上的好强，我尝试了下也碰到这个问题，用楼上的方法，解决了。非常感谢。不过，这与想法有点不同，斑竹能说明下原因么？？为何要把状态设置在状态e上。而且,当状态设置在状态d上，为何只出现一个短脉冲。我估计这肯定与状态改变的瞬时有关。

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