基于CPLD的十字路口交通灯设计
本帖最后由 fpgaw 于 2010-11-23 17:35 编辑基于CPLD的十字路口交通灯设计
说明：
横向红灯纵向绿灯30秒；
横向红灯纵向黄灯5秒；
横向黄灯纵向红灯5秒；
横向绿灯纵向红灯50秒（假设横向的车流量大，所以通行时间长）；
横向黄灯纵向红灯5秒；
横向红灯纵向黄灯5秒。
（循环上述步骤）。
RTL视图：（四个模块一目了然）
芯片：alter公司的MAX II 系列EPM240T100C5
Verilog代码：（由于特权同学的键盘前两天被折腾了，有部分字母按键失灵，所以写程序的时候是软硬键盘一起使，郁闷的直接连注释都省了。）
（顶层模块）
module traffic(clk,rst,row,light_v,led,ledseg);
input clk;
input rst;
output row; // NWSE
output light_v; //red,yellow,green
output led;
output ledseg;
wire light0_reg,light1_reg;
wire second;
wire clk_50k;
wire count;
clk1000div clk1000div( .clk(clk),
.rst(rst),
.clk_50k(clk_50k));
clkdiv clkdiv( .clk(clk),
.rst(rst),
.second(second));
light light( .rst(rst),
.second(second),
.light0_reg(light0_reg),
.light1_reg(light1_reg),
.count(count));
light_dislight_dis( .clk(clk_50k),
.rst(rst),
.count(count),
.light0_reg(light0_reg),
.light1_reg(light1_reg),
.row(row),
.light_v(light_v),
.led(led),
.ledseg(ledseg));
endmodule
(该模块是1000分频产生50KHz信号，主要用于液晶或者交通灯的动态显示定时)
module clk1000div(clk,rst,clk_50k);
input clk;
input rst;
output clk_50k;
reg div;
reg clk_50k;
always @ (posedge clk) begin
if(!rst) begin
div <= 0;
clk_50k <= 0;
end
else begin
if(div==999) begin
clk_50k <= ~clk_50k;
div <= 0; end
else begin
div <= div+1; end
end
end
endmodule
(1Hz分频模块，用于交通灯的定时)
module clkdiv(clk,rst,second);
input clk;
input rst;
output second;
reg num;
reg second;
always @ (posedge clk) begin
if(!rst) begin
num <= 0;
second <= 0;
end
else begin
num <= num+28'd1;
if(num==28'h2faf080) begin
second <= ~second;
num <= 0;
end
end
end
endmodule
（该模块主要用于计算倒计时数值和交通灯的排选）
module light(rst,second,light0_reg,light1_reg,count);
input rst;
input second;
output light0_reg,light1_reg;
output count;
reg count;
reg state;
reg light0_reg,light1_reg;
always @ (posedge second) begin
if(!rst) begin
state <= 0;
end
else begin
if(state == 7'd99) begin
state <= 0;
end
else begin
state <= state+1; end
end
end
always @ (state) begin
if(state<30) begin
count <= 29-state;
light0_reg <= 3'b001;
light1_reg <= 3'b100;
end
if(state>29 && state<35) begin
count <= 34-state;
light0_reg <= 3'b010;
light1_reg <= 3'b100;
end
if(state>34 && state<40) begin
count <= 39-state;
light0_reg <= 3'b100;
light1_reg <= 3'b010;
end
if(state>39 && state<90) begin
count <= 89-state;
light0_reg <= 3'b100;
light1_reg <= 3'b001;
end
if(state>89 && state<95) begin
count <= 94-state;
light0_reg <= 3'b100;
light1_reg <= 3'b010;
end
if(state>94 && state<100) begin
count <= 99-state;
light0_reg <= 3'b010;
light1_reg <= 3'b100;
end
end
endmodule
（该模块进行数码管倒计时显示和交通灯显示控制）
module light_dis(clk,rst,count,light0_reg,light1_reg,row,light_v,led,ledseg);
input clk;
input rst;
input count;
input light0_reg,light1_reg;
output led;
output ledseg;
output row; // NWSE
output light_v; // red,yellow,green
reg row; // NWSE
reg light_v; // red,yellow,green
reg state;
reg led;
reg ledseg;
reg ledreg;
reg led_shu;
always @ (posedge clk) begin
if(!rst) begin
state <= 0;
led_shu <= 8'h3f;
led_shu <= 8'h06;
led_shu <= 8'h5b;
led_shu <= 8'h4f;
led_shu <= 8'h66;
led_shu <= 8'h6d;
led_shu <= 8'h7d;
led_shu <= 8'h07;
led_shu <= 8'h7f;
led_shu <= 8'h6f;
end
else begin
state <= state+1;
if(count<10) begin
ledreg <= led_shu;
ledreg <= led_shu;
end
else if(count<20) begin
ledreg <= led_shu;
ledreg <= led_shu;
end
else if(count<30) begin
ledreg <= led_shu;
ledreg <= led_shu;
end
else if(count<40) begin
ledreg <= led_shu;
ledreg <= led_shu;
end
else begin
ledreg <= led_shu;
ledreg <= led_shu;
end
end
end
always @ (state) begin
case (state)
0: begin
row <= 4'b0101;
light_v <= light0_reg;
led <= 6'b111110;
ledseg <= ledreg;
end
1: begin
row <= 4'b1010;
light_v <= light1_reg;
led <= 6'b111101;
ledseg <= ledreg;
end
default: ;
endcase
end
endmodule 还是很模糊。。。 模糊看不清 四个模块看不清，能解释一下为什么是两个输入，和四个输出吗？ 先看看.................. 初学者 路过 谢谢楼主分享
初学者，学习下
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