新人有个VHDL编程错误，无法理解，求指导
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity top is
generic (n:integer:=16);
port (clk : in std_logic;
clr : in std_logic;
ena: in std_logic;
di: in std_logic_vector(7 downto 0);
do: out std_logic_vector(7 downto 0));
end top;
architecture rtl of top is
component countern
port(clr,ena,clk:in std_logic;
q:buffer integer range 0 to n-1:=0;
cout: out std_logic);
end component;
component rom
port(addr: in integer range 0 to n-1;
clk: in std_logic;
data: out std_logic_vector(7 downto 0));
end component;
component XZQ
port(d0: in std_logic_vector(7 downto 0);
d1: in integer range 0 to n-1;
sel: in std_logic;
yout: out std_logic_vector(7 downto 0));
end component;
component ram
port (ad: in std_logic_vector(7 downto 0);
clk : in std_logic;
di: in std_logic_vector(7 downto 0);
do: out std_logic_vector(7 downto 0);
wr_en: in std_logic:='0';
rd_en: in std_logic:='0');
end component;
signal qs:integer range 0to n-1:=0;
signal ds:std_logic_vector(7 downto 0);
signal ys:std_logic_vector(7 downto 0);
signal cout:std_logic;
signal wr_en:std_logic:='0';
signal rd_en:std_logic:='0';
signal sel:std_logic:='1';
begin
ct:countern
port map(clk=>clk,
clr=>clr,
ena=>ena,
cout=>cout,
q=>qs);
rom0:rom
port map(clk=>clk,
addr=>qs,
data=>ds);
mux:XZQ
port map (d1=>qs,
d0=>ds,
sel=>sel,
yout=>ys);
ram0:ram
port map(clk=>clk,
do=>do,
di=>di,
wr_en=>wr_en,
rd_en=>rd_en,
ad=>ys);
process(cout)
begin
if cout'event and cout='0' then
sel <=not sel;
end if;
if sel='1' then
wr_en<='1';
else
rd_en<='1';
end if;
end process;
end rtl;
这是两个错误，不是正式的端口宽度的实例化的实体声明兼容。
Error: Actual width (4) of port "d1" on instance "XZQ:mux" is not compatible with the formal port width (1) declared by the instantiated entity
Error: Actual width (4) of port "q" on instance "countern:ct" is not compatible with the formal port width (8) declared by the instantiated entity
那我应该怎么改？ 错误：端口实际宽度（4）“D1”的实例“XZQ：MUX”是不是跟正式的端口宽度（1）通过实例化的实体宣告兼容
错误：端口实际宽度（4）“Q”的实例“countern：克拉”是不是跟正式的端口宽度（8）通过实例化的实体宣告兼容 zhiweiqiang33 发表于 2014-4-17 11:55
错误：端口实际宽度（4）“D1”的实例“XZQ：MUX”是不是跟正式的端口宽度（1）通过实例化的实体宣告兼容
...
那么我应该怎么改？ 端口实际宽度（4）“D1”的实例“XZQ：MUX”是不是跟正式的端口宽度（1）端口不一致；
zhiweiqiang33 发表于 2014-4-17 12:01
端口实际宽度（4）“D1”的实例“XZQ：MUX”是不是跟正式的端口宽度（1）端口不一致；
还是不懂，我才学习这个，小白能请大神耐心指导一下么？就比如源程序发上来了，端口宽度应该怎么看。 这个是conuntern的代码。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity countern is
generic(n:integer:=16);
port(clr,ena,clk : in std_logic;
q:buffer integer range 0 to n-1;
cout:out std_logic);
end countern;
architecture rtl of countern is
begin process(clk,clr)
begin
if clr='1' then
q<=0;
else
if clk='1'and clk'event then
if ena='1' then
if q=q'high then
q<=0;
else q<=q+1;
end if;
end if;
end if;
end if;
if q=q'high then
cout<='1';
else
cout<='0';
end if;
end process;
end rtl;
这个是xzq的代码。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity XZQ is
generic (n:integer:=16);
port (d0 : in std_logic_vector(7 downto 0);
d1: in integer range 0 to -1;
sel:in std_logic;
yout:out std_logic_vector(7 downto 0));
end XZQ;
architecture if_march of XZQ is
begin
process(d0,d1,sel)
begin
if(sel='1')then
yout<=conv_std_logic_vector(d1,8);
else
yout<=d0;
end if;
end process;
end if_march; laokai 发表于 2014-4-17 12:20
位宽不匹配原因，
请把下边两个模块的代码帖出来
component countern
我发出来了。 laokai 发表于 2014-4-17 14:52
XZQ的代码接口 d1: in integer range 0 to -1;--这里错误你少了n，按照你第一贴的错误提示应该countern ...
是的，我改过来了。我做的是一个矩阵交织器。可还是不能实现功能，现在正在纠结。
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