Verilog多个模块怎么整合到一块，然后通过下载线下载到FPGA里边呢，谢谢
大家好，这是我在书上找的几个模块，都用Quartus编译通过了，但是我现在要把他们整合在一起，实现一个完整的功能，在Quartus上该怎么做呢，谢谢大家了DS18B20的温度测量模块
module temperature(clk,dq,d,cont,temp);
input clk;
input dq;
output d;
output cont;
output temp;
reg d;
reg cont;
reg temp;
reg data;
reg num;
reg count;
reg t;
always @(posedge clk)
begin
num=num+1;
if(num>'b1000100)
begin num='b0000000;
if(count=='b1001011)
begin count='b0000000;end
else
begin count=count+1;end
end
else
begin num=num+1;end
if(count>='b0000000&&count<='b0000110)
begin data=0;cont=0;end
else if(count>'b0000110&&count<='b0001101)
begin cont<=0;end
else if(count=='b0001110||count=='b0001111||count=='b0010010||count=='b0010011)
begin
if(num>='b0000000&&num<'b0111100)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0010000||count=='b0010001||count=='b0010100||count=='b0010101)
begin
if(num>='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0010110||count=='b0010111||count=='b0011001||count=='b0011010||count=='b0011011||count=='b0011101)//convert'0'
begin
if(num>='b0000000&&num<'b0111100)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0011000||count=='b0011100)
begin
if(num>='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count>='b0011110&&count<='b0100100)
begin data=0;cont=0;end
else if(count>='b0100101&&count<='b0101011)
begin cont=0;end
else if(count=='b0101100||count=='b0101101||count=='b0110000||count=='b0110001)
begin
if(num>='b0000000&&num<'b0111100)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0101110||count=='b0101111||count=='b0110010||count=='b0110011)
begin
if(num>='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0110100||count=='b0111010)
begin
if(num>='b0000000&&num<'b0111100)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0110101||count=='b0110110||count=='b0110111||count=='b01110000||count=='b0111001||count=='b0111011)
begin
if(num>='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
end
else if(count=='b0111100)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b0111101)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b0111110)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b0111111)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000000)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000001)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000010)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000011)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000100)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
else if(count=='b1000101)
begin
if(num<='b0000000&&num<'b0001010)
begin data=0;cont=1;end
else
begin cont=0;end
if(num=='b0001110)
begin t=dq;end
end
d=data;
temp=t;
end
endmodule
温度显示模块
module Two_to_ten(temp,inte_ten,inte_one,deci_ten,deci_one,dot);
input temp;
output inte_ten;
output inte_one;
output deci_ten;
output deci_one;
output dot;
reg inte_ten;
reg inte_one;
reg deci_ten;
reg deci_one;
reg dot;
reg t;
reg deci;
reg inte;
always @(inte,deci,t,temp)
begin
dot<=1;
begin t<=temp;end
inte<=t;
deci<=t;
if(inte<'b011110)
begin
if(inte>='b001010)
begin
if(inte>='b010100)
begin inte_ten<='b0010;
if(inte=='b010100)
begin inte_one<='b0000;end
if(inte=='b010101)
begin inte_one<='b0001;end
if(inte=='b010110)
begin inte_one<='b0010;end
if(inte=='b010111)
begin inte_one<='b0011;end
if(inte=='b011000)
begin inte_one<='b0100;end
if(inte=='b011001)
begin inte_one<='b0101;end
if(inte=='b011010)
begin inte_one<='b0110;end
if(inte=='b011011)
begin inte_one<='b0111;end
if(inte=='b011100)
begin inte_one<='b1000;end
if(inte=='b011101)
begin inte_one<='b1001;end
end
else
begin inte_ten<='b0001;
if(inte=='b001010)
begin inte_one<='b0000;end
if(inte=='b001011)
begin inte_one<='b0001;end
if(inte=='b001100)
begin inte_one<='b0010;end
if(inte=='b001101)
begin inte_one<='b0011;end
if(inte=='b001110)
begin inte_one<='b0100;end
if(inte=='b001111)
begin inte_one<='b0101;end
if(inte=='b010000)
begin inte_one<='b0110;end
if(inte=='b01001)
begin inte_one<='b0111;end
if(inte=='b010010)
begin inte_one<='b1000;end
if(inte=='b010011)
begin inte_one<='b1001;end
end
end
else
begin inte_ten<='b0000;inte_one<=inte;end
end
else if(inte>='b110010)
begin
if(inte>='b111100)
begin inte_ten<='b0110;
if(inte=='b111100)
begin inte_one<='b0000;end
else if(inte=='b111101)
begin inte_one<='b0001;end
else if(inte=='b111110)
begin inte_one<='b0010;end
else if(inte=='b111111)
begin inte_one<='b0011;end
end
else
begin inte_ten<='b0101;
if(inte=='b110010)
begin inte_one<='b0000;end
else if(inte=='b110011)
begin inte_one<='b0001;end
else if(inte=='b110100)
begin inte_one<='b0010;end
else if(inte=='b110101)
begin inte_one<='b0011;end
else if(inte=='b110110)
begin inte_one<='b0100;end
else if(inte=='b110111)
begin inte_one<='b0101;end
else if(inte=='b111000)
begin inte_one<='b0110;end
else if(inte=='b111001)
begin inte_one<='b0111;end
else if(inte=='b111010)
begin inte_one<='b1000;end
else if(inte=='b111011)
begin inte_one<='b1001;end
end
end
else if(inte>='b101000)
begin
inte_ten<='b0100;
if(inte>='b101000&&inte<='b101111)
begin inte_one<=inte;inte_one<='b0;end
else if(inte=='b110000)
begin inte_one<='b1000;end
else if(inte=='b110001)
begin inte_one<='b1001;end
end
else
begin
inte_ten<='b0011;
if(inte=='b011110)
begin inte_one<='b0000;end
else if(inte=='b011111)
begin inte_one<='b0001;end
else if(inte=='b100000)
begin inte_one<='b0010;end
else if(inte=='b100001)
begin inte_one<='b0011;end
else if(inte=='b100010)
begin inte_one<='b0100;end
else if(inte=='b100011)
begin inte_one<='b0101;end
else if(inte=='b100100)
begin inte_one<='b0110;end
else if(inte=='b100101)
begin inte_one<='b0111;end
else if(inte=='b100110)
begin inte_one<='b1000;end
else if(inte=='b100111)
begin inte_one<='b1001;end
end
if(deci=='b1)
begin
if(deci=='b1)
begin
if(deci=='b1)
begin
if(deci=='b1)
begin deci_ten<='b1001;deci_one<='b0100;end
else
begin deci_ten<='b1000;deci_one<='b1000;end
end
else if(deci=='b1)
begin deci_ten<='b1000;deci_one<='b0001;end
else
begin deci_ten<='b0111;deci_one<='b0101;end
end
else if(deci=='b1)
begin
if(deci=='b1)
begin deci_ten<='b0110;deci_one<='b1001;end
else
begin deci_ten<='b0110;deci_one<='b0011;end
end
else if(deci=='b1)
begin deci_ten<='b0101;deci_one<='b0110;end
else
begin deci_ten<='b0101;deci_one<='b0000;end
end
else if(deci=='b1)
begin
if(deci=='b1)
begin
if(deci=='b1)
begin deci_ten<='b0100;deci_one<='b0100;end
else
begin deci_ten<='b0011;deci_one<='b1000;end
end
else if(deci=='b1)
begin deci_ten<='b0011;deci_one<='b0001;end
else
begin deci_ten<='b0010;deci_one<='b0101;end
end
else if(deci=='b1)
begin
if(deci=='b1)
begin deci_ten<='b0001;deci_one<='b1001;end
else
begin deci_ten<='b0001;deci_one<='b0011;end
end
else if(deci=='b1)
begin deci_ten<='b0000;deci_one<='b0110;end
else
begin deci_ten<='b0000;deci_one<='b0000;end
end
endmodule
BCD--七段译码模块
module seven(i,y);
input i;
output y;
reg y;
always @(i)
begin
case(i)
'b0000:y<='b1111110;
'b0001:y<='b0110000;
'b0010:y<='b1101101;
'b0011:y<='b1111001;
'b0100:y<='b0110011;
'b0101:y<='b1011011;
'b0110:y<='b1011111;
'b0111:y<='b1110000;
'b1000:y<='b1111111;
'b1001:y<='b1111011;
default:y<='b1111111;
endcase
end
endmodule
麻烦大家了，帮帮我，老师说要我把他们三个整合到一块，然后仿真时序，最后做实测，说做不出来，就让我延期毕业，痛苦啊，谢谢谢谢大家了
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