后仿真时的问题，求大神解决
# Options:#
# -mindelays Use minimum timing from min:typ:max expressions
#
# -typdelays Use typical timing from min:typ:max expressions (default)
#
# -maxdelays Use maximum timing from min:typ:max expressions
#
# -delayscale <val> Scale delays by the specified value
#
# -nocompress Don't compress the resulting output file
#
# -suppress <msg(s)>Suppress comma-separed list of error/warning messages
#
# Loading work.CYCLONE_PRIM_DFFE
# ** Warning: (vsim-SDF-3445) Failed to parse SDF file "frequence_divider_8_v.sdo".
# Time: 0 psIteration: 0Instance: /tb_frequence_divider_8 File: E:/fpga project/frequence_divider_8/sim/tb_frequence_divider_8
# Error loading design
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