七段顯示器在DE2可當成Verilog的console，做為16進位的輸出結果。
Verilog / SWITCH_SEG7.v1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : SWITCH_SEG7.v
5 Compiler : Quartus II 7.2 SP1
6 Description : Demo how to use 8 bit 7 segment display
7 Release : 04/16/2008 1.0
8 */
9 module SWITCH_SEG7 (
10 //Host side
11 input CLOCK_50, // 50 MHz
12 inputKEY,
13 input SW,
14 output HEX0,
15 output HEX1,
16 output HEX2,
17 output HEX3,
18 output HEX4,
19 output HEX5,
20 output HEX6,
21 output HEX7
22 );
23
24 SEG7_LUT_8 u0 (
25 .oSEG0(HEX0),
26 .oSEG1(HEX1),
27 .oSEG2(HEX2),
28 .oSEG3(HEX3),
29 .oSEG4(HEX4),
30 .oSEG5(HEX5),
31 .oSEG6(HEX6),
32 .oSEG7(HEX7),
33 .iDIG(SW),
34 .iWR(1'b1),
35 .iCLK(CLOCK_50),
36 .iRESET_n(KEY)
37 );
38
39 endmodule
這是top module，主要將switch的值傳入iDIG，iWR是個enable，這裡沒特別用到，就傳1'b1即可。
Verilog / SWITCH_LUT.v
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : SWITCH_LUT.v
5 Compiler : Quartus II 7.2 SP1
6 Description : Demo how to use 8 bit 7 segment display
7 Release : 04/16/2008 1.0
8 */
9 module SEG7_LUT (
10 input iDIG,
11 output reg oSEG
12 );
13
14 always@(iDIG) begin
15 case(iDIG)
16 4'h1: oSEG = 7'b1111001;// ---t----
17 4'h2: oSEG = 7'b0100100;// | |
18 4'h3: oSEG = 7'b0110000;// lt rt
19 4'h4: oSEG = 7'b0011001;// | |
20 4'h5: oSEG = 7'b0010010;// ---m----
21 4'h6: oSEG = 7'b0000010;// | |
22 4'h7: oSEG = 7'b1111000;// lb rb
23 4'h8: oSEG = 7'b0000000;// | |
24 4'h9: oSEG = 7'b0011000;// ---b----
25 4'ha: oSEG = 7'b0001000;
26 4'hb: oSEG = 7'b0000011;
27 4'hc: oSEG = 7'b1000110;
28 4'hd: oSEG = 7'b0100001;
29 4'he: oSEG = 7'b0000110;
30 4'hf: oSEG = 7'b0001110;
31 4'h0: oSEG = 7'b1000000;
32 endcase
33 end
34
35 endmodule
這是一個七段顯示器的lookup table。
Verilog / SWITCH_LUT8.v
1 /*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : SWITCH_LUT8.v
5 Compiler : Quartus II 7.2 SP1
6 Description : Demo how to use 8 bit 7 segment display
7 Release : 04/16/2008 1.0
8 */
9 module SEG7_LUT_8 (
10 output oSEG0,
11 output oSEG1,
12 output oSEG2,
13 output oSEG3,
14 output oSEG4,
15 output oSEG5,
16 output oSEG6,
17 output oSEG7,
18 input iDIG,
19 input iWR,
20 input iCLK,
21 input iRESET_n
22 );
23
24 reg dig;
25
26 always@(posedge iCLK or negedge iRESET_n) begin
27 if (!iRESET_n)
28 dig <= 0;
29 else begin
30 if (iWR)
31 dig <= iDIG;
32 end
33 end
34
35 SEG7_LUT u0 (
36 .iDIG(dig),
37 .oSEG(oSEG0),
38 );
39
40 SEG7_LUT u1 (
41 .iDIG(dig),
42 .oSEG(oSEG1)
43 );
44
45 SEG7_LUT u2 (
46 .iDIG(dig),
47 .oSEG(oSEG2)
48 );
49
50 SEG7_LUT u3 (
51 .iDIG(dig),
52 .oSEG(oSEG3)
53 );
54
55 SEG7_LUT u4 (
56 .iDIG(dig),
57 .oSEG(oSEG4)
58 );
59
60 SEG7_LUT u5 (
61 .iDIG(dig),
62 .oSEG(oSEG5)
63 );
64
65 SEG7_LUT u6 (
66 .iDIG(dig),
67 .oSEG(oSEG6)
68 );
69
70 SEG7_LUT u7 (
71 .iDIG(dig),
72 .oSEG(oSEG7)
73 );
74
75 endmodule
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