QuartusII编译与仿真之warning大解析 10
22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew原因:使用了行波时钟或门控时钟,把触发器的输出当时钟用就会报行波时钟, 将组合逻辑的输出当时钟用就会报门控时钟
措施:不要把触发器的输出当时钟,不要将组合逻辑的输出当时钟,如果本身如 此设计,则无须理会该警告
23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments
原因: 一个always模块中同时有阻塞和非阻塞的赋值
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