DDS任意信号发生器
/*信号定义
inclock:时钟
control:控制产生波形的种类，为00,01,10,11时，分别产生正弦波、方波、三角波和锯齿波；
i：控制读取时间间隔，调整频率
q_out:输出数据*/
module signal_gene(inclock,q_out,control,i);
input inclock;
output q_out;
input control;//控制产生波形的种类
input i;
reg address;
wire q_out;
reg m,k;
reg state;
rom rom_component(.address(address),
.clock(inclock),
.q(q_out)
);
always @(posedge inclock)
begin
case(state)
0:begin //产生正弦波形
if(control==1) address<=9'd128;
if(control==2) address<=9'd256;
if(control==3) address<=9'd384;
if(i==0||i==1) begin
address<=address+1'b1;
if(address>=9'd127) address<=9'd0;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=m) address<=9'd0;
end
end
1:begin //产生锯齿波形
if(control==0)address<=9'd0;
if(control==2)address<=9'd256;
if(control==3)address<=9'd384;
if(address<128) address<=9'd128;
else begin
if(i==0||i==1)begin
address<=address+1'b1;
if(address==9'd255) address<=9'd128;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=m+9'd128) address<=9'd128;
end
end
end
2:begin//产生方波形
if(control==0)address<=9'd0;
if(control==1) address<=9'd128;
if(control==3)address<=9'd384;
if(address<9'd256) address<=9'd256;
else begin
if(i==0||i==1)begin
address<=address+1'b1;
if(address==9'd383) address<=9'd256;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=m+256) address<=9'd256;
end
end
end
3:begin //产生三角波形
if(control==1) address<=9'd128;
if(control==2) address<=9'd256;
if(control==3) address<=9'd384;
if(address<384) address<=9'd384;
else begin
if(i==0||i==1) begin
address<=address+1'b1;
if(address==9'd511) address<=9'd384;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=m+384) address<=9'd384;
end
end
end
endcase
end
endmodule
测试文件：
`timescale 1 ps/ 1 ps
module signal_gene_vlg_tst();
reg control;
reg i;
reg inclock;
// wires
wire q_out;
// assign statements (if any)
signal_gene i1 (
// port map - connection between master ports and signals/registers
.control(control),
.i(i),
.inclock(inclock),
.q_out(q_out)
);
initial
begin
inclock=0;
i=4'b0000;
control=2'b00;
#100 control=2'b11;
#100 control=2'b10;
#100000 $finish;
end
always#10 inclock=~inclock;
endmodule
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