做一个按键自加自减的程序，出现了显示问题。
顶层文件module led_jj_seg(
input clock ,
input reset ,
input key1 ,
input key2 ,
output seg_led_a,
output seg_led_b,
output seg_led_c,
output seg_led_d,
output seg_led_e,
output seg_led_f,
output seg_led_g,
output seg_led_dp,
output seg_led_dig1,
output seg_led_dig2,
output seg_led_dig3,
output seg_led_dig4,
output LED
);
// *************************
// SIGNALS
// *************************
wire counter;
wire seg_s;
wire seg;
//wire clock_200hz;
//wire clock_10hz;
assign LED = 4'b0000;
// *************************
// CODE
// *************************
// *************************
// SUBMODULE
// *************************
led_jj u_led_jj(
.clock (clock) ,
.reset (reset) ,
.counter (counter) ,
.key1 (key1) ,
.key2 (key2)
);
dyn_seg u_dyn_seg (
.clock (clock_200hz),
.reset (reset),
.data (counter),
.seg_s (seg_s),
.seg (seg)
);
// clk_gen u_clk_gen(
// .clock (clock) ,
// .reset (reset) ,
// .clock_200hz(clock_200hz) ,
// .clock_10hz (clock_10hz)
// );
assign seg_led_a = seg;
assign seg_led_b = seg;
assign seg_led_c = seg;
assign seg_led_d = seg;
assign seg_led_e = seg;
assign seg_led_f = seg;
assign seg_led_g = seg;
assign seg_led_dp = seg;
assign seg_led_dig1 = seg_s;
assign seg_led_dig2 = seg_s;
assign seg_led_dig3 = seg_s;
assign seg_led_dig4 = seg_s;
endmodule
自加、自减文件
module led_jj(
input clock ,
input reset ,
input key1 ,
input key2 ,
output reg counter
);
reg key_xiaodou;
reg key_xiaodou_yanchi;
reg count;
reg key_cunchu;
reg key_cunchu_yanchi;
reg temp;
wire key_xiaodou_chucun;
wire key_cunchu_chucun;
always @(posedge clock or negedge reset)
begin
if(!reset)begin
key_xiaodou <= 2'b11;
key_xiaodou_yanchi <= 2'b11;
end
else begin
key_xiaodou <= {key2,key1};
key_xiaodou_yanchi <= key_xiaodou;
end
end
assign key_xiaodou_chucun = key_xiaodou_yanchi & (~key_xiaodou);
always @(posedge clock or negedge reset)
begin
if(!reset)
count <= 20'd0; //测试下位宽改变有无影响
else if(key_xiaodou_chucun)
count <= 20'd0;
else
count <= count+1'd1;
end
always @(posedge clock or negedge reset)
begin
if(!reset)begin
key_cunchu <= 2'b11;
key_cunchu_yanchi <= 2'b11;
end
else if(count == 20'hfffff)begin
key_cunchu <= {key2,key1};
end
else begin
key_cunchu_yanchi <= key_cunchu;
end
end
assign key_cunchu_chucun = key_cunchu_yanchi & (~key_cunchu);
always @ (posedge clock or negedge reset)
begin
if (!reset) begin
counter <= 14'b0;
end
else begin
if (counter==14'd9999) begin
counter <= 14'b0;
end
else begin
temp = key_cunchu_chucun;
case(temp)
2'b01 : counter <= counter+14'b1 ;
2'b10 : counter <= counter-14'b1 ;
default:;
endcase
end
end
end
endmodule
显示文件
//****************************************Copyright 2014************************// *
// ************************Declaration***************************************//
// File name: dyn_seg.v //
// Author: buck.feng@link-real.com.cn //
// Date: 2014-03-21 15:18 //
// Version Number: 1.0 //
// Abstract:
// Modification history: //
// 2014-03-21 15:18 version 1.0 xxx //
// Abstract: Initial //
// //
// *********************************end************************************** //
`timescale 1ns/100ps
// *************************
// MODULE DEFINTION
// *************************
module dyn_seg(
input clock ,
input reset ,
input data ,
outputreg seg_s ,
outputreg seg
);
// *************************
// SIGNALS
// *************************
reg count_show ;
wire data0 ;
wire data1 ;
wire data2 ;
wire data3 ;
reg hex ;
// *************************
// CODE
// *************************
assign data0 = data/1000;
assign data1 = data%1000/100;
assign data2 = data%100/10;
assign data3 = data%10;
always @ (negedge reset or posedge clock)
begin
if (!reset) begin
count_show <= 2'b0;
end
else begin
count_show <= count_show+2'b1;
end
end
always @ (negedge reset or posedge clock)
begin
if(!reset) begin
seg_s <= 4'b0;
end
else begin
case(count_show)
2'b00 : seg_s <= 4'b0001;
2'b01 : seg_s <= 4'b0010;
2'b10 : seg_s <= 4'b0100;
2'b11 : seg_s <= 4'b1000;
default: ;
endcase
end
end
always @ (*)
begin
case(count_show)
2'b00 : hex <= data0;
2'b01 : hex <= data1;
2'b10 : hex <= data2;
2'b11 : hex <= data3;
default:hex <= 4'b0;
endcase
end
always @ (negedge reset or posedge clock)
begin
if (!reset) begin
seg <= 8'b0;
end
else begin
case(hex)
4'h0: seg <= 8'b11000000;
4'h1: seg <= 8'b11111001;
4'h2: seg <= 8'b10100100;
4'h3: seg <= 8'b10110000;
4'h4: seg <= 8'b10011001;
4'h5: seg <= 8'b10010010;
4'h6: seg <= 8'b10000010;
4'h7: seg <= 8'b11111000;
4'h8: seg <= 8'b10000000;
4'h9: seg <= 8'b10010000;
4'hA: seg <= 8'b01110111;
4'hB: seg <= 8'b01111100;
4'hC: seg <= 8'b00111001;
4'hD: seg <= 8'b01011110;
4'hE: seg <= 8'b01111001;
4'hF: seg <= 8'b01110001;
default: ;
endcase
end
end
//// *************************
//// SUBMODULE
//// *************************
endmodule
程序在上面，但是显示出来后 数码管的数字不对 试一试把二进制转bcd码模块改一下，直接相除取余速度是非常慢的
页:
[1]
