数字信号采集 串口 FPGA 遇到问题求大神指点
我想实现数字信号采集，并通过串口发送出去，能用串口接收上位机指令，控制采集。下面是我用quartus ii 软件编的程序，但是不好使，请大神指点！module yiwei(clk1,in8,en,rst1,out8,rclk,ren,rx);
input clk1,en;
input rst1;
input in8;
input rclk;
input ren;
output out8;
output rx;
reg cnt;
reg Q;
wire line8;
regWREG;
regRREG;
reg wen;
initial Q=0;
assign out8=Q;
always @(posedge clk1 or negedge rst1)
if(!rst1)
begin
Q<=0;
end
else if(en)
begin
Q<=in8;
end
always @(posedge clk1 or negedge rst1)
if(!rst1) WREG=0;
else if(en)
begin
if(WREG<8)
WREG<=WREG+1;
else WREG<=0;
end
else WREG<=0;
always @(posedge rclk)
if(ren)
begin
if(RREG<8)
RREG<=RREG+1;
else RREG<=0;
end
else RREG<=0;
arm4 my_ram(
.data(out8),
.rdaddress(RREG),
.rdclock(rclk),
.rden(ren),
.wraddress(WREG),
.wrclock(clk1),
.wren(en),
.q(line8)
);
UART_RX myRX(
.sys_clk(rclk),
.reset_rx,
.Rx_start(ren),
.Rx(rx),
.Rx_Data(line8),
.Rx_Reg()
);
endmodule
子模块
module UART_RX(
sys_clk,reset_rx,Rx_start,Rx,Rx_Data,Rx_Reg
);
input sys_clk,reset_rx,Rx,Rx_start;
output Rx_Reg;
output Rx_Data;
regRx_Data;
reg Rx_Reg;
parameter SYS_CLK=50000000;//50M系统时钟
parameter Rx_bps=9600;
parameter Rxdata_w=12;
parameter RXCLK_DATA=SYS_CLK/Rx_bps-1;//波特率分频器分频值
reg clk_cnt;
reg EN_RXCLK;
wire RX_CLK; //波特率时钟
always @(posedge sys_clk or negedge reset_rx)
if(!reset_rx)
clk_cnt<=12'd0;
else if(!EN_RXCLK)
clk_cnt<=12'd0;
else if(clk_cnt==RXCLK_DATA)
clk_cnt<=12'd0;
else clk_cnt<=clk_cnt+1;
assign RX_CLK=(clk_cnt==0);//产生发送时钟
reg RxState;
reg RxTemp;//
always @(posedge sys_clk or negedge reset_rx)
if(!reset_rx)
begin
RxState=4'd0;
Rx_Data=8'd0;
RxTemp=10'd0;//
Rx_Reg=1'b0;
EN_RXCLK=1'b0;
end
else if((Rx_Reg==0)&&(RxState==0)&&Rx_start)
begin
EN_RXCLK=1'b1;
RxState<=4'd1;
end
else if(RX_CLK)
begin
case(RxState)
4'd1: begin
RxTemp<=Rx;
RxState<=4'd2;
end
4'd2:begin
RxTemp<=Rx;
RxState<=4'd3;
end
4'd3:begin
RxTemp<=Rx;
RxState<=4'd4;
end
4'd4:begin
RxTemp<=Rx;
RxState<=4'd5;
end
4'd5:begin
RxTemp<=Rx;
RxState<=4'd6;
end
4'd6:begin
RxTemp<=Rx;
RxState<=4'd7;
end
4'd7:begin
RxTemp<=Rx;
RxState<=4'd8;
end
4'd8:begin
RxTemp<=Rx;
RxState<=4'd9;
end
4'd9:begin
RxTemp<=Rx;//结束位
RxState<=4'd0;
EN_RXCLK<=1'b0;
if(RxTemp)
begin
Rx_Data<=RxTemp;
Rx_Reg=1'b1;
end
end
endcase
end
else Rx_Reg=1'b0;
endmodule
还有这个模块
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: arm4.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module arm4 (
data,
rdaddress,
rdclock,
rden,
wraddress,
wrclock,
wren,
q);
input data;
input rdaddress;
input rdclock;
input rden;
input wraddress;
input wrclock;
input wren;
output q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 rden;
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire q = sub_wire0;
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 128,
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK1",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "128"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "128"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q"
// Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress"
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress"
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL arm4_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf 大神如果有可以实现此功能的程序就更好了，我编的可能有一些问题。
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