TimeQuest Example: Multicycle Exceptions
本帖最后由 王建飞 于 2015-9-1 14:58 编辑With the Synopsys Design Constraint (SDC) command set_multicycle_path, you can specify the number of allowable clock cycles, with respect to either the destination or source clock, for the data to propagate between the source and destination registers. This is useful in the scenario shown in Figure 1.
Figure 1 shows a simple circuit where a multicycle of 2 is required for the destination register reg2. Register reg2 should latch that data every second clock cycle.
#Constrain the base clock
create_clock -period 10.000
#Constrain the PLL output clock
create_generated_clock -source inst|inclk -multiply_by 2 \
-name inst|clk inst|clk
#Constrain the input and output ports
set_input_delay -clock clk_in 1.2
set_input_delay -clock clk_in 1.5
set_output_delay -clock clk_in 2
#Apply a multicycle of 2 to registers reg1 and reg2
#By default the multicycle is relative to the destination clock waveform
set_multicycle_path -setup -end -from -to 2
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement
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