TimeQuest Example: Constraining Generated Clocks
With the Synopsys Design Constraint (SDC) command create_generated_clock, you can create arbitrary numbers and depths of generated clocks. This is useful in the following scenarios. See Figures 1 and 2.Figure 1 shows a simple circuit where a generated clock is required at the output of register div2reg.
The SDC commands below constrain the clocks in the above circuit.
#Constrain the base clock
create_clock -add -period 10.000 \
-waveform { 0.000 5.000 } \
-name clock_name \
#Constrain the divide by 2 register clock
create_generated_clock -add -source clock \
-name div2clock \
-divide_by 2 \
-master_clock clock_name \
Download example circuit create_generated_clock_ex1.qar.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement.
Figure 2 shows a simple circuit where a generated clock is required at the output of register div2reg.
The SDC commands below constrain the clocks in the above circuit.
#Constrain the base clock
create_clock -add -period 10.000 \
-waveform { 0.000 5.000 } \
-name clock_name \
#Constrain the output clock clock
create_generated_clock -add -source PLL_inst|inclk \
-name PLL_inst|clk \
-multiply_by 2 \
-master_clock clock_name \
]
Download example circuit create_generated_clock_pll.qar.
The use of this design is governed by, and subject to, the terms and conditions of the Altera Hardware Reference Design License Agreement
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