FPGA时序改善代码，参悟
1 module randomlogic_1(2 output reg Out,
3 input A, B, C,
4 input clk,
5 input Cond1, Cond2);
6 always @(posedge clk)
7 if(Cond1)
8 Out <= A;
9 else if(Cond2 && (C < 8))
10 Out <= B;
11 else
12 Out <= C;
13 endmodule
复制代码
第二版：
复制代码
1 module randomlogic_2(
2 output reg Out,
3 input A, B, C,
4 input clk,
5 input Cond1, Cond2);
6
7 wire CondB = (Cond2 & !Cond1);
8
9 always @(posedge clk)
10 if(CondB && (C < 8))
11 Out <= B;
12 else if(Cond1)
13 Out <= A;
14 else
15 Out <= C;
16 endmodule
页:
[1]
