本人初学VHDL,所以不是很熟悉。
我用ISE仿真的时候提示" Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
听说是要给输出信号赋初值,可是怎么赋初值?在哪里赋初值。。。真的不懂。。。。。求指点。。。。
程序如下:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity kilometers is
Port ( RESET : in STD_LOGIC;
CLKOUT : in STD_LOGIC;
KM_CNT0 : out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT1 : out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT2 : out STD_LOGIC_VECTOR (3 downto 0);
KM_CNT3 : out STD_LOGIC_VECTOR (3 downto 0));
end kilometers;
architecture Behavioral of kilometers is
SIGNAL CNT0:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT2:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CNT3:STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(RESET,CLKOUT)
BEGIN
IF RESET='1'
THEN CNT0<="0000";
CNT1<="0000";
CNT2<="0000";
CNT3<="0000";
ELSIF CLKOUT'EVENT AND CLKOUT='1'
THEN IF CNT3="1001" AND CNT2="1001" AND CNT1="1001" AND CNT0="1001"
THEN CNT0<="0000";
CNT1<="0000";
CNT2<="0000";
CNT3<="0000";
ELSIF CNT3/="1001" AND CNT2="1001" AND CNT1="1001" AND CNT0="1001"
THEN CNT0<="0000";
CNT1<="0000";
CNT2<="0000";
CNT3<=CNT3+"0001";
ELSIF CNT2/="1001" AND CNT1="1001" AND CNT0="1001"
THEN CNT0<="0000";
CNT1<="0000";
CNT2<=CNT2+"0001";
CNT3<=CNT3;
ELSIF CNT1/="1001" AND CNT0="1001"
THEN CNT0<="0000";
CNT1<=CNT1+"0001";
CNT2<=CNT2;
CNT3<=CNT3;
ELSIF CNT0/="1001"
THEN CNT0<=CNT0+"0001";
CNT1<=CNT1;
CNT2<=CNT2;
CNT3<=CNT3;
END IF ;
END IF ;
KM_CNT0<=CNT0;
KM_CNT1<=CNT1;
KM_CNT2<=CNT2;
KM_CNT3<=CNT3;
END PROCESS;
end Behavioral;
听说是要给输出信号赋初值,可是怎么赋初值?在哪里赋初值。。。