VHDL流水灯设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity liushui is
port(
clk:IN std_logic;
clr:IN std_logic;
ena:IN std_logic;
yut std_logic_vector (7 downto 0) );
end;
architecture behave of liushui is
begin
signal y_out:std_logic_vector(7 downto 0); process(clk,clr,ena) if clr = '0' then y_out<= "00000001"; elsif clk'event and clk = '1' then if ena = '1' then y_out <= y_out<<1; end if; end if;end process; y <= y_out; end behave;

VHDL流水灯设计

VHDL流水灯设计