怎么理解这句话

wire  clk_5ms=&count;

& : This is a bitwise-AND operator. It performs an AND function on
the operands to return a value that is equivalent in bus width to the
operands.

参考资料:  <<Verilog.Coding.for.Logic.Synthesis>> a john Wiley & sons. publish

------count的所有位进行“与”运算，结果赋给clk_5ms;

我重新看了书，原来是缩减运算··