always @ (posedge CLK)
begin
if(!rst_n)
begin
cnt <=0;
low_sw <= 1'b1;
low_sw_r <= 1'b1;
end
else if(cnt==`DELAY)
begin
cnt<=0;
low_sw <= sw_n; //?20ms?????????low_sw?
low_sw_r <= low_sw;
end
else
begin
cnt<=cnt+1'b1;
low_sw_r <= low_sw;
end
end
endmodule