ISE中常见WARNING和ERROR及其解决方法

1."WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew  
because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK  
template."  

Solution  
This message informs the user that some loads on the clock net are not  
clock pins. Therefore, the clock template that is normally used to connect  
clock pins will not be used to connect the loads. A different routing that  
involves local routing will be used, potentially inducing some skew on the  
clock net.
      Opening your design in FPGA EDITOR will allow you to see what loads are  
connected to the clock net, and the cause of the warnings.
      The amount of skew on the net will be reported in the Place and Route  
report.
      If the loads on the net shown in FPGA Editor are in accord with your  
design, the skew reported in the PAR report is not critical for the  
design, and the timing constraint requirement on that net is met, then  
this warning can be safely ignored.
      实例原因：在代码中用到这样的语句时（aa’event and  
aa=’1’），aa不是时钟信号，最多只是时钟信号产生的一类周期信号，aa被作为了另一个
进程或模块的类似周期信号的作用。（我是在行场信号发生器中 出现的这样的问题，用产
生的行同步信号（行同步信号是由全局时钟信号驱动产生的）再去驱动产生场同步信号，产
生的场同步信号相对与输入的全局时钟，有一定 的倾斜）

2. "WARNING:Xst:647 - Input <name> is never used."  
or  
"WARNING:Xst:648 - Output <name> is never used."

Solution  
This particular port has been declared in your HDL description, but does  
not drive or is not driven by any internal logic.
      Unused input ports will remain in the design, but they will be completely  
unconnected. If the port is not intended to be used, this message can be  
safely ignored. To avoid this message, remove any loadless or sourceless  
elements from your HDL description.
      Output ports will remain in the final netlist and will be driven by a  
logic 0. To avoid the message and to save the port resource, remove the  
unused output port from your HDL description.
      实例原因：一般输入端口不要预留，即使不使用，在代码中定义的输入端口就一定要有
输入的； 而输出端口不用到的可以用OPEN封上， 最常见的是在利用DLL和DCM时， CLK90，
CLK180，
      CLK270等一般不用，在端口连接的时候都用 OPEN封上。       3. ERROR:HDLParsers:3562 - pepExtractor.prj line 1 Expecting 'vhd ' or  
'verilog' keyword, found 'work'。SolutionThis occurs when there are spaces  
embedded in the project location.
      A bad example for project location would be:  
C:/Documents and Settings/User/example.ise.
      A good example fpr project location would be:  
C:/ISE_tests/example.ise.
      实例原因：在 ISE9.1的版本里，在行为仿真和使用约束编辑器的时候会遇到，主要原
因是工程的路径名里有空格一类的不被要求的非英文字符。
      4. "ERROR:Xst:2587 Port <port_name> of instance <inst_name> has different  
type in definition <def_name>" .
      Solution  
Compare the component declaration and instantiation to the submodule that  
is instantiated. When this error occurs, the declaration matches the  
instantiation, but does not match the port declarations of the submodule.
      Change either the port declarations in the declaration/instantiation pair  
or the submodule port declarations so that they match. This error is  
specific to the types of ports in the submodule.
      实例原因：一般是子模块宣称和子模块的实体定义中端口的宽度和类型(in, out, inout,
buffer)不匹配造成的。
      5. XST can generate very large log files for certain designs. In some  
cases, the generation of these log files can even cause an increase in  
runtime. How can I eliminate or hide certain frequently generated  
messages?
      Solution  
For users of XST via Project Navigator
      Starting in ISE 7.1i, Project Navigator has the capability to do message  
filtering for all Xilinx tools. Please refer to the Project Navigator help  
on how to use this method.
      For users of XST via command line
      You can hide specific messages generated by XST at the HDL or Low-Level  
Synthesis steps in specific situations by using the XIL_XST_HIDEMESSAGES  
environment variable. This environment variable can have one of the  
following values:
      -- none: maximum verbosity. All messages are printed out. This is the  
default.  
-- hdl_level: reduce verbosity during VHDL/Verilog Analysis and HDL Basic  
and Advanced Synthesis.  
-- low_level: reduce verbosity during Low-level Synthesis  
-- hdl_and_low_levels: reduce verbosity at all stages
      The following messages are hidden when hdl_level or hdl_and_low_levels  
values are specified for the XIL_XST_HIDEMESSAGES environment variable:
      WARNING:HDLCompilers:38 - design.v line xx Macro 'my_macro' redefined  
NOTE: This message is issued by the Verilog compiler only.       WARNING:Xst:916 - design.vhd line xx: Delay is ignored for synthesis.
      WARNING:Xst:766 - design.vhd line xx: Generating a Black Box for component  
comp.
      Instantiating component comp from Library lib.
      Set user-defined property "LOC = X1Y1" for instance inst in unit block.
      Set user-defined property "RLOC = X1Y1" for instance inst in unit block.
      Set user-defined property "INIT = 1" for instance inst in unit block.
      Register reg1 equivalent to reg2 has been removed.
      The following messages are hidden when low_level or hdl_and_low_levels  
values are specified for the XIL_XST_HIDEMESSAGES environment variable:
      WARNING:Xst:382 - Register reg1 is equivalent to reg2.
      Register reg1 equivalent to reg2 has been removed.
      WARNING:Xst:1710 - FF/Latch reg (without init value) is constant in block  
block.
      WARNING:Xst 1293 - FF/Latch reg is constant in block block.
      WARNING:Xst:1291 - FF/Latch reg is unconnected in block block.
      WARNING:Xst:1426 - The value init of the FF/Latch reg hinders the constant  
cleaning in the block block. You could achieve better results by setting  
this init to value.
      实例原因：在综合时，有很多的综合警告是可以忽略的，以上大致的罗列几项。
      6. "WARNING:Xst:737 - Found n-bit latch for signal <name>."
      The listing for "n" is the width of the latch.
      If latch inference is intended, you can safely ignore this message.  
However, some inefficient coding styles can lead to accidental latch  
inference. You should analyze your code to see if this result is intended.  
The examples below illustrate how you can avoid latch inference.
      实例原因：一般出现这样的问题都是代码出现了锁存器，因避免这样的代码写法，电路
会不稳定，因利用触发器去寄存数据在时钟沿。
      Solution 1  
Include all possible cases in the case statement
      Verilog  
always @ (SEL or DIN1 or DIN2)  
begin  
case (SEL)  
2'b00 : DOUT <= DIN1 + DIN2;  
2'b01 : DOUT <= DIN1 - DIN2;  
2'b10 : DOUT <= DIN1;  
endcase  
end
      VHDL  
process (SEL, DIN1, DIN2)  
begin  
case SEL is  
when "00" => DOUT <= DIN1 + DIN2;  when "01" => DOUT <= DIN1 - DIN2;  
when "10" => DOUT <= DIN1;  
end case;  
end process;
      These two examples create latches because there is no provision for the  
case when SEL = "11." To eliminate the latches, add another entry to deal  
with this possibility.
      Verilog  
2'b11 : DOUT <= DIN2;
      VHDL  
when "11" => DOUT <= DIN2;
      Using the "DEFAULT" (Verilog) or "WHEN OTHERS" (VHDL) clause always works,  
but this can create extraneous logic. This is always the safest  
methodology, but might produce a larger and slower design since any  
unknown state has logic that is needed to bring it to a known state.
      Solution 2  
Assign to all the same outputs in each case.
      Verilog  
always @ (SEL or DIN1 or DIN2)  
begin  
case (SEL)  
2'b00 : DOUT <= DIN1 + DIN2;  
2'b01 : DOUT <= DIN1 - DIN2;  
2'b10 : DOUT <= DIN1;  
2'b11 :  
begin  
DOUT <= DIN2;  
TEMP <= DIN1;  
end  
endcase  
end
      VHDL  
process (SEL, DIN1, DIN2)  
begin  
case SEL is  
when "00" => DOUT <= DIN1 + DIN2;  
when "01" => DOUT <= DIN1 - DIN2;  
when "10" => DOUT <= DIN1;  
when "11" =>  
DOUT <= DIN2;  
TEMP <= DIN1;  
end case;  
end process;       These examples infer latches because the "11" case assigns two outputs,  
while the others assign only one. Looking at this case from TEMP's point  
of view, only one of four possible cases are specified, so it is  
incomplete. You can avoid this situation by assigning values to the exact  
same list of outputs for each case.
      Solution 3  
Make sure any "if / else if" statements have a concluding "else" clause:
      VHDL:  
process (ge, din)  
begin  
if (ge = '1') then  
dout_a <= din;  
else  
dout_a <= '0';                               -- This is a concluding  
"else" statement.  
end if;  
end process;
Verilog:  
always @(ge or din)  
if (ge) dout_a <= din;  
else dout_a <= 1'b0;                        // This is a concluding "else"  
statement.  
在不影响电路功能的情况下，要写完整的 if--else语句。（对于时钟沿触发时，是不要 else
的)

7.ERRORlace:1018 - A clock IOB / clock component pair have been found that are not
placed at an optimal clock IOB / clock site pair. The clock component <CLK16_inst> is
placed at site <BUFGMUX_X0Y3>. The IO component <Ref_Clk_p> is placed at site
<A8>.  This will not allow the use of the fast path between the IO and the Clock buffer. If
this sub optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override is highly
discouraged as it may lead to very poor timing results. It is recommended that this error
condition be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the .ucf file to
override this clock rule. < NET "Ref_Clk_p" CLOCK_DEDICATED_ROUTE = FALSE; >

解决方法：CLK16_inst 和 Ref_Clk 只都用 BUFG，或都用 IBUFG.(个人验证解决问题，但
不保证一定解决问题)

8.WARNINGhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
Flash_rst_n is set but the tri state is not configured.  
Your problem is in the source code,not your constraints.  It's
complainingthat you don't ever tristate the signal, either because your equations
don't have a tristate term or because that term has been optimised away.
就是非输入加上拉后，没有配置三态。这是程序的出错，不关 constraints。

顶,
楼主如何封端口？
给个例子

什么封端口？

蓝余版主，上面的意思可能是：如何进行引脚约束？？？（个人理解）