modelsim 和verilog-xl有没有本质上的不同？

modelsim 和verilog-xl有没有本质上的不同？

做pre_layout时序仿真时，发现一个问题：同样的库文件，同样的testbench文件
，同样的SDF文件，利用modelsim仿真没有报告任何错误信息，而在工作站上用verilog-xl仿真
则报告很多错误

下面的这些错误信息如何去解释？谢了先
maxx.sdf  maxx.sdf  L18462: SDFA Error: Unable to find source port test_maxxtime.MAXX.db1d[0]
          maxx.sdf  L18463: SDFA Error: Unable to find source port test_maxxtime.MAXX.db2d[0]
          maxx.sdf  L18464: SDFA Error: Unable to find source port test_maxxtime.MAXX.db1d[1]
          maxx.sdf  L18465: SDFA Error: Unable to find source port test_maxxtime.MAXX.db2d[1]
          maxx.sdf  L18466: SDFA Error: Unable to find source port test_maxxtime.MAXX.db1d[2]
          maxx.sdf  L18467: SDFA Error: Unable to find source port test_maxxtime.MAXX.db2d[2]
          maxx.sdf  L19161: SDFA Warning: Negative timing check limit -0.240000 set to 0
          maxx.sdf  L19162: SDFA Warning: Negative timing check limit -0.310000 set to 0
          maxx.sdf  L19165: SDFA Warning: Negative timing check limit -0.390000 set to 0
          maxx.sdf  L19166: SDFA Warning: Negative timing check limit -0.420000 set to 0
          maxx.sdf  L19171: SDFA Warning: Negative timing check limit -0.500000 set to 0
          maxx.sdf  L19172: SDFA Warning: Negative timing check limit -0.350000 set to 0