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module spi(
in_rst_n ,
in_we_n ,
in_wdata ,
in_clk ,
in_spi_en ,
out_spi_csn ,
out_spi_dat ,
out_sck ,
out_mode ,
// out_int
);
//G4
input in_rst_n ;
input in_we_n ;
input [15:0] in_wdata ;
//output out_int ;
//codec
input in_clk ;
input in_spi_en;
output out_spi_csn ;
output out_spi_dat ;
output out_sck ;
output out_mode ;
reg out_rdata ;
reg [4:0] count ;
reg [15:0] spi_dat ;
//reg out_int ;
reg spi_csn ;
reg en_en ;
reg div2_clk ;
reg div4_clk ;
reg div8_clk ;
wire spi_en_en ;
reg in_spi_en1 ;
wire in_spi_en ;
wire [15:0] in_wdata ;
wire in_clk ;
wire in_rst_n ;
wire in_we_n ;
wire read ;
wire write ;
wire out_mode ;
wire spi_en ;
always @(negedge in_clk)
in_spi_en1 <= in_spi_en;
assign spi_en_en = in_spi_en & (~in_spi_en1);
always @(negedge in_clk or negedge in_rst_n)
begin
if(!in_rst_n)
div2_clk <= 0;
else
div2_clk <= ~div2_clk;
end
always @(negedge div2_clk or negedge in_rst_n)
begin
if(!in_rst_n)
div4_clk <= 0;
else
div4_clk <= ~div4_clk;
end
always @(negedge div4_clk or negedge in_rst_n)
begin
if(!in_rst_n)
div8_clk <= 0;
else
div8_clk <= ~div8_clk;
end
assign spi_en = in_spi_en & en_en ;
//always @(negedge in_clk or negedge in_rst_n)
always @(negedge in_clk or posedge spi_en_en)
begin
if(spi_en_en)
count <= 0;
else
if(count > 18)
count <= 0;
else
if(spi_en)
count <= count + 1 ;
else
count <= count;
end
//always @(negedge in_clk or negedge in_rst_n)
always @(negedge in_clk or posedge spi_en_en)
begin
if(spi_en_en)
spi_csn <= 1 ;
else if((count>0) && (count<17))
spi_csn <= 0 ;
else spi_csn <= 1;
end
wire out_spi_csn = spi_csn ;
//always @(negedge in_clk or negedge in_rst_n)
always @(negedge in_clk or posedge spi_en_en)
begin
//if(spi_en_en)
// spi_dat <= 16'b0 ;
//else
if(!in_we_n)
spi_dat <= in_wdata ;
else if(!spi_csn)
spi_dat[15:1] <= spi_dat[14:0] ;
end
assign out_spi_dat = spi_dat[15];
//always @(negedge in_clk or negedge in_rst_n)
always @(negedge in_clk or posedge spi_en_en)
begin
if(spi_en_en)
begin
en_en <= 1'b1;
end
else
if(count==18)
begin
en_en <= 1'b0 ;
end
end
wire out_sck = div8_clk;
assign out_mode = 1'b1;
endmodule
还有个I2C模块,太长了,在我博客http://blog.sina.com.cn/s/blog_4b19994d0100sxe7.html |
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