always @ (posedge clk50M, posedge rst)
begin
case (state)
S0 :
begin
cnt<=cnt+32'd1;
if (cnt == 32'd49)
begin
state <= S1;
cnt<=32'd0;
end
else
state <= S0;
end
S1 :
begin
if(rst==1)
begin
rdaddress<=3'd0;
end
else
begin
rden<=1'b1;
wr<=1'b0;
rdaddress<=rdaddress+4'd1;
if(rdaddress == 4'd15)
begin
rdaddress <= 4'd0;
rden<=1'b0;
wr<=1'b1;
state <= S0;