如何将自己写的verilog模块封装成IP核

平台与材料
一个写好的工程，综合通过，不用布局布线，ISE或Vivado皆可。如果是ISE，需要在properties里取消选中 iobuf 。这样就只能被当做内部模块调用了。
Vivado
步骤
打开Vivado，创建一个工程
Tools -> Create or package IP
里面有三个选项，分别是打包本工程，打包本工程的一个Design，打包一个目录下的工程。
一般会选第三个。
在该目录下，应该有一个Vivado或者ISE工程，综合通过了的。
选择完打包的目录后，选择Automatically select top module。
一般都能选择到正确的top module，如果选错了，先查看文件是否全部导入，如果全部导入了还选错顶层模块，那就右键手动set as top。
这个时候在右上侧的代码视窗里应该出现了配置IP核的选项，有好几种，慢慢选，完了在最后一栏检查有没错漏，然后点package IP。
然后IP就生成好了，在Block Design的原理图视窗右键add IP，就能找到你刚刚打包的IP了。


官方解释：
Description
There is a black-box submodule in the design which is fed with an EDIF/NGC netlist. The following errors and warnings are issued during Translate:

"ERROR:NgdBuild:770 - IBUF 'b_IBUF' and IBUF 'b_ibuf' on net 'b_IBUF' are linedup in series. Buffers of the same direction cannot be placed in series.
WARNING:NgdBuild:463 - input pad net 'b_IBUF' has an illegal input buffer
ERROR:NgdBuild:925 - input net 'b_IBUF' is connected to the incorrect side ofbuffer(s):
pin O on block b_IBUF with type IBUF
ERROR:NgdBuild:924 - input pad net 'clk_BUFGP' is driving non-buffer primitives:
pin C on block h with type FDR, pin C on block g with type FD, pin O on block clk_BUFGP/BUFG with type BUFG
ERROR:NgdBuild:809 - output pad net 'e' has an illegal load:
pin I1 on block Mxor_g_xor0000_Result1 with type LUT2
ERROR:NgdBuild:455 - logical net 'h' has multiple driver(s):
pin Q on block h with type FDR, pin PAD on block h.PAD with type PAD"

How can I resolve these errors?

Solution
These errors are issued because the submodule EDIF/NGC netlist contains IBUFs/OBUFs. XST also adds IBUFs and OBUFs to the top level, so that they are lined up or the pads are driving/being driven by non-buffer components.

When an EDIF/NGC netlist is used as a submodule of another design, the following conditions must be met:

If the input/output ports of the submodule are connected to the top module ports directly, like port1in the following figure, the IBUFs/OBUFs can be put in the submodule,but theXST property "Read Cores"has tobe checked. Then,XSTwill read the netlistin the project directory or a location specified in "Cores Search Directories" and will not add extra IBUFs/OBUFs on these top level ports.
If theinput/output ports of the submodule are NOT connected to the top module ports directly, like port2 inthe following figure, the IBUFs/OBUFs must not be put in the submodule.

The following are some solutions to this problem.

Disable IBUF/OBUF insertion when you generate the submodule netlist. Add all IBUFs/OBUFsto the top level.
For XST, go to Synthesis Properties -> Xilinx Specific Options -> uncheck "Add I/O Buffers"
For Synplify Pro, go to Implementation Options -> Device tab -> check "Disable I/O Insertion"
Selectively disableIBUF/OBUF insertion onthe input/output ports that are NOT connected to the top module ports directly.
For XST, use "buffer_type" constraint. Please refer to XST User Guide.
For Synplify Pro, refer to (Xilinx Answer 4508).
If theIBUF/OBUFs are instantiated in the submodule, disablingIBUF/OBUF insertiondoes not remove the buffers from the submodule. If this is the case, remove theIBUF/OBUFs instantaiation from the submodule and instantiate them in the top level.

如何将自己写的verilog模块封装成IP核
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如何将自己写的verilog模块封装成IP核