ed2板子 fpga vga显示程序出问题，请高手指点呀，多谢了

module vvg(clock, switch, r,g,b,hsync,vsync,vgablank,vgasync);
input  clock;
input  [1:0]switch;
output [9:0]r;
output [9:0]g;
output [9:0]b;
output  hsync;
output  vsync;
output vgablank;
output vgasync;
reg [9:0] hcount;
reg [9:0] vcount;
reg  hsync;
reg  vsync;
reg [2:0] data;
reg [2:0] h_dat;
reg [2:0] v_dat;
reg  vga_clk;
wire [9:0]r;
wire [9:0]g;
wire [9:0]b;
parameter
   hs_Ta= 10'd96,//hs_Tb=10'd40,hs_Tc=10'd8,hs_Td=10'd640,hs_Te=10'd8,hs_Tf=10'd8,
   hdat_begin  = 10'd144,
   hdat_end  = 10'd784,
   pixel_end  = 10'd800,
   vs_ta= 10'd2,//vs_Tb=10'd25,vs_Tc=10'd8,vs_Td=10'd480,vs_Te=10'd8,vs_Tf=10'd2,vs_Ta=10'd2,
   vdat_begin  = 10'd35,
   vdat_end  = 10'd515,
   line_end  = 10'd525;
//signal timer
always @(posedge clock)
begin
vga_clk = ~vga_clk;
end
//make the hsync  signal
always @(posedge vga_clk)
begin
if (hcount<pixel_end-1'b1)
  hcount <= hcount + 10'd1;
else
  hcount <= 10'd0;
end

always @(posedge vga_clk)
begin
if(hcount>=hs_Ta)
hsync=1'b1;
else
hsync=1'b0;
end
//make the vsync signal
always @(negedge hsync)
begin
if (vcount<line_end-1'b1)
vcount<=vcount+10'd1;
else
vcount<=10'd0;
end

always @(negedge hsync)
begin
if(vcount>=vs_ta)
vsync=1'b1;
else
vsync=1'b0;
end


always @(posedge vga_clk)
begin
case(switch[1:0])
  2'd0: data <= h_dat;      //选择横彩条
  2'd1: data <= v_dat;      //选择竖彩条
  2'd2: data <= (v_dat ^ h_dat); //产生棋盘格
  2'd3: data <= (v_dat ~^ h_dat); //产生棋盘格
endcase
end
assign vgablank=hsync||vsync,vgasync=1'b0;
always @(posedge vga_clk)
begin
if(hcount < hdat_begin+80)
  v_dat <= 3'd7;   //白   
else if(hcount <hdat_begin+160)
  v_dat <= 3'd6;   //黄
else if(hcount <hdat_begin+240)
  v_dat <= 3'd5;   //青
else if(hcount <hdat_begin+320)
  v_dat <= 3'd4;    //绿
else if(hcount <hdat_begin+400)
  v_dat <= 3'd3;   //紫
else if(hcount <hdat_begin+480)
  v_dat <= 3'd2;   //红
else if(hcount <hdat_begin+560)
  v_dat <= 3'd1;   //蓝
else
  v_dat <= 3'd0;   //黑
end

always @(posedge vga_clk)  //产生横彩条
begin
if(vdat_begin<vcount<=vdat_begin+60)
  h_dat <= 3'd7;    //白
else if(vcount <=vdat_begin+120)
  h_dat <= 3'd6;   //黄
else if(vcount <=vdat_begin+180)
  h_dat <= 3'd5;   //青
else if(vcount <=vdat_begin+240)
  h_dat <= 3'd4;    //绿
else if(vcount <=vdat_begin+300)
  h_dat <= 3'd3;   //紫
else if(vcount < vdat_begin+360)
  h_dat <= 3'd2;   //红
else if(vcount <=vdat_begin+420)
  h_dat <= 3'd1;   //蓝
else
  h_dat <= 3'd0;   //黑
end
assign {r[9],g[9],b[9]}=data;
assign {r[8],g[8],b[8]}=data;
assign {r[7],g[7],b[7]}=data;
assign {r[6],g[6],b[6]}=data;
assign {r[5],g[5],b[5]}=data;
assign {r[4],g[4],b[4]}=data;
assign {r[3],g[3],b[3]}=data;
assign {r[2],g[2],b[2]}=data;
assign {r[1],g[1],b[1]}=data;
assign {r[0],g[0],b[0]}=data;
endmodule