verilog hdl仿真不知道哪里出问题，求大侠帮助。

Error: Cannot route source node "lpm_counter:q2_rtl_1|alt_counter_f10ke:wysi_counter|q[2]" of type logic cell to destination node "q2[2]" of type I/O pin
Error: Cannot route source node "lpm_counter:q2_rtl_1|alt_counter_f10ke:wysi_counter|q[2]" of type logic cell to destination node "always1~61" of type logic cell
Error: Cannot route source node "lpm_counter:q5_rtl_3|alt_counter_f10ke:wysi_counter|q[2]" of type logic cell to destination node "q5[2]" of type I/O pin
Error: Cannot route source node "lpm_counter:q5_rtl_3|alt_counter_f10ke:wysi_counter|q[2]" of type logic cell to destination node "Equal4~58" of type logic cell
Error: Can't find fit

我觉得像管脚分配哪里有问题，你可以找找。
前提是语法没问题。