我用的是ise11.1版本，时序仿真不出现结果，不知道是为什么啊？

我是带着问题来的 想请高手们指点啊。

我用的是ise11.1版本，芯片是xilinx spartan3an系列的 xc3s700an，在时序约束后出现下面的warning，时序仿真不出现结果，不知道是为什么啊？

具体如下：

WARNINGhysDesignRules:372 - Gated clock. Clock net adc_OBUF is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
WARNING:Timing:3175 - clk does not clock data to cp
WARNING:Timing:3225 - Timing constraint COMP "cp" OFFSET = OUT 1000 ns AFTER COMP "clk" REFERENCE_PIN BEL "adc"; ignored
   during timing analysis
WARNING:Timing:3224 - The clock clk associated with OFFSET = OUT 13 ns AFTER COMP "clk"; does not clock any registered
   output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 13 ns AFTER COMP "clk"; ignored during timing analysis
WARNING:Timing:3224 - The clock clk associated with TIMEGRP "grp_ado" OFFSET = OUT 1000 ns AFTER COMP "clk"
   REFERENCE_PIN BEL        "adc" "RISING"; does not clock any registered output components.
WARNING:Timing:3225 - Timing constraint TIMEGRP "grp_ado" OFFSET = OUT 1000 ns AFTER COMP "clk" REFERENCE_PIN BEL      
   "adc" "RISING"; ignored during timing analysis
WARNING:Route:455 - CLK Net:adc_OBUF may have excessive skew because     1 CLK pins and 1 NON_CLK pins failed to route using a CLK template.
WARNING:Timing:3175 - clk does not clock data to cp
WARNING:Timing:3225 - Timing constraint COMP "cp" OFFSET = OUT 1000 ns AFTER
   COMP "clk" REFERENCE_PIN BEL "adc"; ignored during timing analysis
WARNING:Timing:3224 - The clock clk associated with OFFSET = OUT 13 ns AFTER COMP "clk"; does not clock any registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 13 ns AFTER COMP "clk";
   ignored during timing analysis
WARNING:Timing:3224 - The clock clk associated with TIMEGRP "grp_ado" OFFSET =
   OUT 1000 ns AFTER COMP "clk" REFERENCE_PIN BEL        "adc" "RISING"; does
   not clock any registered output components.
WARNING:Timing:3225 - Timing constraint TIMEGRP "grp_ado" OFFSET = OUT 1000 ns
   AFTER COMP "clk" REFERENCE_PIN BEL        "adc" "RISING"; ignored during
   timing analysis