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利用中值滤波的的思想,调用模板1 2 1 实现
2 4 2
1 2 1
module gslb(din,clk,clrb,a1,a2,a3,a4,a5,a6,a7,a8,a9,dout1,dout2,dout3);
input[7:0] din;
input clk,clrb;
output [7:0] a1,a2,a3,a4,a5,a6,a7,a8,a9,dout1,dout2,dout3;
reg [7:0]a1,a2,a3,a4,a5,a6,a7,a8,a9,dout1,b1,b2,b3,b4,b5,b6,b7,b8,b9;
reg wrreq1,rdreq1,wrreq2,rdreq2;
wire[7:0]dout2,dout3;
reg [15:0]counter;
always @(posedge clk or negedge clrb)
begin
if(!clrb) counter<=0;
else counter<=counter+1;
end
always @(posedge clk or negedge clrb)
begin
if(!clrb)
dout1<=0;
else
begin
if(counter==2) wrreq1<=1;
if(counter==4) rdreq1<=1;
if(counter==6) wrreq2<=1;
if(counter==8) rdreq2<=1;
if(counter%6==2 && counter>=8)
begin
a3<=0;
a6<=0;
a9<=0;
a1<=b1;
a2<=b2;
a4<=b4;
a5<=b5;
a7<=b7;
a8<=b8;
end
else
begin
a1<=b1;a2<=b2;a3<=b3;a4<=b4;a5<=b5;a6<=b6;a7<=b7;a8<=b8;a9<=b9;end
if(counter%6==1 && counter>=8)
begin
a1<=0;
a4<=0;
a7<=0;a2<=b2;a3<=b3;a5<=b5;a6<=b6;a8<=b8;a9<=b9;
end
else
begin a1<=b1;a2<=b2;a3<=b3;a4<=b4;a5<=b5;a6<=b6;a7<=b7;a8<=b8;a9<=b9;end
if(counter>=9)
dout1<=(a1+a3+a7+a9+(a2+a4+a6+a8)*2+a5*4)/16;
end
end
shift_3 shift1(.din(din),.clk(clk),.clrb(clrb),.q0(b1),.q1(b2),.q2(b3));
myfifo u1(.clock(clk),.data(b3),.rdreq(rdreq1),.wrreq(wrreq1),.empty(),.full(),.q(dout2),.usedw());
shift_3 shift2(.din(dout2),.clk(clk),.clrb(clrb),.q0(b4),.q1(b5),.q2(b6));
myfifo u2(.clock(clk),.data(b6),.rdreq(rdreq2),.wrreq(wrreq2),.empty(),.full(),.q(dout3),.usedw());
shift_3 shift3(.din(dout3),.clk(clk),.clrb(clrb),.q0(b7),.q1(b8),.q2(b9));
endmodule
为什么这一段没有被执行呀
if(counter%6==2 && counter>=8)
begin
a3<=0;
a6<=0;
a9<=0;
a1<=b1;
a2<=b2;
a4<=b4;
a5<=b5;
a7<=b7;
a8<=b8;
end
else
begin
a1<=b1;a2<=b2;a3<=b3;a4<=b4;a5<=b5;a6<=b6;a7<=b7;a8<=b8;a9<=b9;end |
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