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module train (reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5, switch1, switch2, switch3, dirA, dirB);
input reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5;
output switch1, switch2, switch3;
output [1:0] dirA, dirB;
reg switch1, switch2;
reg [1:0] dirA, dirB;
reg [2:0] state;
parameter ABout = 0, Ain = 1, Bin = 2, Astop = 3, Bstop = 4;
always @(posedge clock or posedge reset)
begin
if (reset)
state = ABout;
else
case (state)
ABout:
case (sensor12)
2'b 00: state = ABout;
2'b 01: state = Bin;
2'b 10: state = Ain;
2'b 11: state = Ain;
default: state = ABout;
endcase
Ain:
case (sensor24)
2'b 00: state = Ain;
2'b 01: state = ABout;
2'b 10: state = Bstop;
2'b 11: state = ABout;
default: state = ABout;
endcase
Bin:
case (sensor13)
2'b 00: state = Bin;
2'b 01: state = ABout;
2'b 10: state = Astop;
2'b 11: state = ABout;
default: state = ABout;
endcase
Astop:
if (sensor3)
state = Ain;
else
state = Astop;
Bstop:
if (sensor4)
state = Bin;
else
state = Bstop;
default: state = ABout;
endcase
end
wire [1:0] sensor12 = {sensor1, sensor2};
wire [1:0] sensor13 = {sensor1, sensor3};
wire [1:0] sensor24 = {sensor2, sensor4};
wire switch3 = 0;
always @(state)
begin
case (state)
ABout:
begin
switch1 = 0;
switch2 = 0;
dirA = 2'b 01;
dirB = 2'b 01;
end
Ain:
begin
switch1 = 0;
switch2 = 0;
dirA = 2'b 01;
dirB = 2'b 01;
end
Bin:
begin
switch1 = 1;
switch2 = 1;
dirA = 2'b 01;
dirB = 2'b 01;
end
Astop:
begin
switch1 = 1;
switch2 = 1;
dirA = 2'b 00;
dirB = 2'b 01;
end
Bstop:
begin
switch1 = 0;
switch2 = 0;
dirA = 2'b 01;
dirB = 2'b 00;
end
default:
begin
switch1 = 0;
switch2 = 0;
dirA = 2'b 00;
dirB = 2'b 00;
end
endcase
end
endmodule |
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