architecture rtl of key_led is
signal count:integer range 0 to 3;
signal q:std_logic;
signal key:std_logic_vector(7 downto 0);
signal keyout_rec:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if(clk 'event and clk='1')then
if(reset='0')then
count<=0;
elsif(q='1')then
if(count=3)then
count<=0;
else
count<=count+1;
end if;
else
null;
end if;
end if;
end process;
process(count)
begin
case count is
when 0=>keyout_rec<="1110";
when 1=>keyout_rec<="1101";
when 2=>keyout_rec<="1011";
when 3=>keyout_rec<="0111";
when others=>null;
end case;
end process;
process(clk)
begin
if(clk 'event and clk='0')then
if(keyin="1111")then
q<='1';
else
q<='0';
end if;
end if;
end process;
key<=keyout_rec&keyin;
keyout<=keyout_rec;
process(key)
begin
case key is
when "01111110"=>data<="11110011";
when "01111101"=>data<="01001001";
when "01111011"=>data<="01100001";
when "01110111"=>data<="00110011";
when "10111110"=>data<="00100101";
when "10111101"=>data<="00000101";
when "10111011"=>data<="11110001";
when "10110111"=>data<="00000001";
when "11011110"=>data<="00100001";
when "11011101"=>data<="00010001";
when "11011011"=>data<="00000111";
when "11010111"=>data<="10001101";
when "11101110"=>data<="01000011";
when "11101101"=>data<="00001101";
when "11101011"=>data<="00011101";
when "11100111"=>data<="10000001";
when others=>null;
end case;
end process;
end rtl;
但是在功能仿真的时候却出现这种情况,data会输出一些case语句中没有的数据(图片附件),实在不明白问题在哪儿,求解啊~~