本帖最后由 fpgaw 于 2010-7-16 14:12 编辑
一个数字跑表程序,clk:时钟信号;clr:异步复位信号;pause:暂停信号;msh,msl:百分秒高位和低位:sh,sl:秒高位和低位;mh,ml:分高位和低位
module paobiao(msh,msl,sh,sl,mh,ml,clk,clr,pause);
output [3:0]msh,msl,sh,sl,mh,ml;
inputclk,clr,pause;
reg [3:0]msh,msl,sh,sl,mh,ml;
reg cn1,cn2; //cn1为百分秒位向秒位进位,cn2为秒位向分位进位
//*********百分秒计数进程,每计满100,cn1产生一个进位**********
always @(posedge clk or posedge clr)
begin
if(clr) //异步复位
begin
{msh,msl}<=8'h00;
cn1<=0;
end
else
if(!pause) //pause为0正常计数,为1暂停计数
begin
if(msl==9)
begin msl<=0;
if(msh==9)
begin msh<=0;cn1<=1; end
else msh=msh+1;
end
else
begin msl=msl+1; cn1<=0; end
end
//*********秒计数进程,每计满60,cn2产生一个进位**********
always @(posedge cn1 or posedge clr)
begin
if(clr) begin
{sh,sl}<=8'h00; cn2<=0;
end
else if(sl==9)
begin sl<=0;
if(sh==5)
begin sh<=0; cn2<=1; end
else sh=sh+1;
end
else
begin sl<=sl+1; cn2<=0; end
end
//*********分位计数进程,每计满100,cn1产生一个进位**********
always @(posedge cn2 or posedge clr)
begin
if(clr)
begin {mh,ml}<=8'h00; end
else
if(ml==9)
begin ml<=0;
if(mh==5) mh<=0;
else mh<=mh+1;
end
else ml<=ml+1;
end
endmodule
错位信息:
Error (10170): Verilog HDL syntax error at paobiao.v(27) near text "always";expecting "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement,
Error (10170): Verilog HDL syntax error at paobiao.v(42) near text "always";expecting "@", or "end", or an identifier ("always" is a reserved keyword ), or a system task, or "{", or a sequential statement,
Error (10170): Verilog HDL syntax error at paobiao.v(54) near text "endmodule";expecting "@", or "end", or an identifier ("endmodule" is a reserved keyword ), or a system task, or "{", or a sequential statement, |