各位帮我看看这代码错误在哪

library lpm;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mydefine.all;
entity lut is
    port(addr:in std_logic_vector(rank downto 0);
          outdata:  out std_logic_vector(7 downto 0);
          clk:in std_logic);
end lut;
architecture beh of lut is
component lpm_rom  ----------调用lpm rom实现查表
  generic(LPM_WIDTH:natural;----必须大于0
          LPM_WIDTHAD:natural;
          LPM_NUMWORDS:natural:=0;
          LPM_ADDRESS_CONTROL:string:="REGISTERED";
          LPM_OUTDATA:string:="REGISTERED";
          LPM_FILE:string;
          LPM_TYPE:string:="LPM_ROM";
          LPM_HINT:string:="UNUSED");
  port(ADDRESS:in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
        INCLOCK:in STD_LOGIC:='0';
        OUTCLOCK:inSTD_LOGIC:='0';
        Q:  out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
      begin
      ul:lpm_rom----匹配各参数和端口
      generic map(8,rank,0,"registered","unregistered","rom.mif ","lpm_rom","unused")
              port map(inclock=>clk,address=>addr,q=>outdata);
end beh;