啥意思？？以前没遇到啊。各位大神，求解答

Error: D:/developTools/xilinx/14.2/ISE_DS/ISE/verilog/src/simprims/X_LATCHE.v(108): $width( posedge CLK:108104616 ps, :108104729 ps, 364 ps )
PR后仿报这错
啥意思？？以前没遇到啊。各位大神，求解答

时序未能够满足