module fd23(clkin,clkout);
input clkin;
output clkout;
reg clkout;
reg[1:0] q2;
reg[1:0] q3;
reg [3:0] clk_10_times;
always@(posedge clkin)
begin
if(clk_10_times<3)
begin
if(q3<2)
begin
q3<=q3+1;
clkout<=0;
end
else
begin
q3<=0;
clkout<=1;
clk_10_times<=clk_10_times+1;
end
end
else if(clk_10_times<10)
begin
if(q2<1)
begin
q2<=q2+1;
clkout<=0;
end
else
begin
q2<=0;
clkout<=1;
clk_10_times<=clk_10_times+1;
if(clk_10_times==9)
clk_10_times<=0;
end
end
end
endmodule