always@(posedge clk)
begin
if(rst)
cnt_reg<=0;
else
cnt_reg<=cnt_reg+1;
end
always@(posedge clk)
begin
if(rst)
light_reg<=4'b001;
else if(cnt_reg==24'hffffff)begin
if(light_reg==4'b1000)
light_reg<=4'b0001;
else
light_reg<=light_reg<<1;
end
end
assign led=light_reg;