Senior Engineer for FPGA 北京铿腾电子科技有限公司上海分公司（Cadence）

发布日期：        2010-04-16        工作地点：        上海-浦东新区        招聘人数：        若干
工作年限：        二年以上        语言要求：        英语 良好        学    历：        本科
职位描述
Position Description:
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.

Position Requirements:
1. The position requires BSEE, or equivalent, with industry experience in designing hardware systems;
2. Technical expertise in FPGA design for either Altera or Xilinx products is required;
3. Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired;
4. In addition RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows;
5. Verification using with Cadence simulation products is desired;
6. Experience with scripting languages like Perl, TCL C-shell is strongly recommended. Experience with PCB tools is also desired;
7. Good English communication skill, both oral and written.
联系方式
电子邮箱：        job_china@cadence.com

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