FPGA学习——数码管之时钟设计

设计一个秒表，分辨率为0.01s，分三个位，分钟位，秒位，毫秒位，前两个是六十进制，后一个是一百进制，写四个文件，一个分频文件，一个10进制计数器，一个六进制计数器，一个数码管的显示文件，实验要用到两个频率，一个时钟频率，产生0.01s的时钟，一个数码管的轮流扫描频率。
程序如下
分频（50M产生100HZ和1K）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FENPING IS
PORT(
CLK:IN STD_LOGIC;
CLK_1K:OUT STD_LOGIC;
CLK_100:OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE ART OF FENPING IS
SIGNAL COUNT:INTEGER RANGE 0 TO 10#49999#;
SIGNAL COUNT1:INTEGER RANGE 0 TO 10#499999#;
BEGIN
PROCESS(CLK)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
  IF(COUNT=10#49999#)THEN COUNT<=0;
   ELSE COUNT<=COUNT+1;
   END IF;
   IF(COUNT1=10#499999#)THEN COUNT1<=0;
   ELSE COUNT1<=COUNT1+1;
   END IF;
END IF;
END PROCESS;
PROCESS(COUNT)IS
BEGIN
IF(COUNT>=10#25000#)THEN
      CLK_1K<='1';
  ELSE CLK_1K<='0';
END IF;
END PROCESS;
PROCESS(COUNT1)IS
BEGIN
IF(COUNT1>=10#250000#)THEN
CLK_100<='1';
ELSE CLK_100<='0';
END IF;
END PROCESS;
END ARCHITECTURE;
六进制计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(
CLK:IN STD_LOGIC;
EN,CLR:IN STD_LOGIC;
CN:OUT STD_LOGIC;
Q6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE ART OF CNT6 IS
SIGNAL TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,EN,CLR)IS
BEGIN
IF(CLR='1')THEN TMP<="0000";
ELSE IF(EN='1')THEN
         IF(CLK'EVENT AND CLK='1')THEN
           IF(TMP="0101")THEN TMP<="0000";CN<='1';
           ELSE TMP<=TMP+1;CN<='0';
           END IF;
         END IF;
       END IF;
END IF;
END PROCESS;
Q6<=TMP;
END ARCHITECTURE;
十进制计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(
CLK:IN STD_LOGIC;
EN,CLR:IN STD_LOGIC;
CN:OUT STD_LOGIC;
Q0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE ART OF CNT10 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
Q0<=TEMP;
PROCESS(CLK,EN,CLR)IS
BEGIN
IF(CLR='1')THEN TEMP<="0000";
ELSE IF(EN='1')THEN
         IF(CLK'EVENT AND CLK='1')THEN
           IF(TEMP="1001")THEN TEMP<="0000";
           ELSE TEMP<=TEMP+1;
           END IF;
         END IF;
       END IF;
END IF;


END PROCESS;

PROCESS(TEMP)IS
BEGIN
IF(TEMP>="0101")THEN CN<='1';
ELSE CN<='0';
END IF;
END PROCESS;
END ARCHITECTURE;
数码管扫描
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHONG IS
PORT(
CLK:IN STD_LOGIC;
CLR,EN:IN STD_LOGIC;
DIS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
SEG:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE ART OF SHIZHONG IS
COMPONENT FENPING IS
PORT(
CLK:IN STD_LOGIC;
CLK_1K:OUT STD_LOGIC;
CLK_100:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT CNT6 IS
PORT(
CLK:IN STD_LOGIC;
EN,CLR:IN STD_LOGIC;
CN:OUT STD_LOGIC;
Q6:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT CNT10 IS
PORT(
CLK:IN STD_LOGIC;
EN,CLR:IN STD_LOGIC;
CN:OUT STD_LOGIC;
Q0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL TEM:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL DIS_TMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DIS_CODE:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL S1,S2,S3,S4,S5,S6:STD_LOGIC;
SIGNAL CLK_1K,CLK_100:STD_LOGIC;
BEGIN
U0:FENPING PORT MAP(CLK,CLK_1K,CLK_100);
U1:CNT10 PORT MAP(CLK_100,EN,CLR,S1,TEM(3 DOWNTO 0));
U2:CNT10 PORT MAP(S1,EN,CLR,S2,TEM(7 DOWNTO 4));
U3:CNT10 PORT MAP(S2,EN,CLR,S3,TEM(11 DOWNTO 8));
U4:CNT6 PORT MAP(S3,EN,CLR,S4,TEM(15 DOWNTO 12));
U5:CNT10 PORT MAP(S4,EN,CLR,S5,TEM(19 DOWNTO 16));
U6:CNT6 PORT MAP(S5,EN,CLR,S6,TEM(23 DOWNTO 20));
PROCESS(SEG)IS
BEGIN
CASE (SEG+1)IS
WHEN"000"=>DIS_TMP<=TEM(23 DOWNTO 20);
WHEN"001"=>DIS_TMP<=TEM(19 DOWNTO 16);
WHEN"010"=>DIS_TMP<="1010";
WHEN"011"=>DIS_TMP<=TEM(15 DOWNTO 12);
WHEN"100"=>DIS_TMP<=TEM(11 DOWNTO 8);
WHEN"101"=>DIS_TMP<="1010";
WHEN"110"=>DIS_TMP<=TEM(7 DOWNTO 4);
WHEN"111"=>DIS_TMP<=TEM(3 DOWNTO 0);
END CASE;
END PROCESS;
PROCESS(DIS_TMP)IS
BEGIN
CASE(DIS_TMP)IS
WHEN"0000"=>DIS_CODE<="00111111";
WHEN"0001"=>DIS_CODE<="00000110";
WHEN"0010"=>DIS_CODE<="01011011";
WHEN"0011"=>DIS_CODE<="01001111";
WHEN"0100"=>DIS_CODE<="01100110";
WHEN"0101"=>DIS_CODE<="01101101";
WHEN"0110"=>DIS_CODE<="01111101";
WHEN"0111"=>DIS_CODE<="00000111";
WHEN"1000"=>DIS_CODE<="01111111";
WHEN"1001"=>DIS_CODE<="01101111";
WHEN"1010"=>DIS_CODE<="01000000";
WHEN OTHERS=>DIS_CODE<="00000000";
END CASE;
END PROCESS;
PROCESS(CLK_1K)IS
BEGIN
IF(CLK_1K'EVENT AND CLK_1K='1')THEN
SEG<=SEG+1;
DIS<=DIS_CODE;
END IF;
END PROCESS;
END ARCHITECTURE;
本实验的难点在于数码管的动态扫描，关键是要把段和位联系起来，每选中一个数码管，就把对应的码值赋给它，动态扫描就是利用人眼的视觉差异来写的，当数码管扫描速度大于24HZ时人眼分辨不了，所以感觉是静态的，扫描速度也不可太快，一般选1K的扫描速度。