求大神帮我讲解这段FPGA代码，谢谢了

begin
sda_choose_r <=1’b1;
scl_choose_r <= 1’b1; //发送模式下将sda和scl都设置为输出
if(delay_time == 13’d0) //scl处于高电平
begin
sda_r_r <= db[bit_count];
end
if(delay_time == 13’d4000) //80us周期已经循环完毕
begin
if(bit_count_next == 11)
begin
bit_count_next <=4’d0;
delay_time_next <= 1’d0;
finish_r <= 1’b1; //当一字节发送完，返回完成标志
send_state <=5’d6;
end
else
begin
bit_count_next <= bit_count +1’b1;
delay_time_next <= 1’b0; //发送未完成就返回未完成标志
end
end
else
delay_time_next = delay_time +1’b1;
end

就是IIC发送数据的顺序

就是IIC发送数据的顺序

                 谢谢