library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fskdec is
generic
(
foneperiod : std_logic_vector(7 downto 0) := "00000111";
ftwoperiod : std_logic_vector(7 downto 0) := "00001111"
);
port(clk : in std_logic;
fskcodein : in std_logic;
dataout : out std_logic);
end fskdec;
architecture behave of fskdec is
signal cnt :std_logic_vector(7 downto 0);
signal datacom : std_logic_vector(1 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
datacom <= fskcodein & datacom(1);
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if datacom = "10" then
if (cnt < foneperiod + "00000010") and (cnt > foneperiod - "00000010") then
dataout <= '0';
cnt <= "00000000";
elsif (cnt < ftwoperiod + "00000010") and (cnt > ftwoperiod - "00000010") then
dataout <= '1';
cnt <= "00000000";
end if;
elsif cnt > (ftwoperiod + "00000001") then
cnt <= "00000000";
else
cnt <= cnt + "00000001";
end if;
end if;
end process;