ISE8.2中遇到问题，求解答！！！
我是一个初学者，第一次按照课本进行操作，当进行到测试平台的编写这一步时，出现了问题进行不下去了，我建的测试文件名为test_one4two1这是自动生成的测试模块代码// Verilog Test Fixture Template
`timescale 1 ns / 1 ps
module TEST_gate;
reg <signal1>;
reg <signal2>;
wire <signal3>;
wire <signal4>;
<module_name> <instance_name> (
<port1>,
<port2>
);
integer <name1>;
integer <name2>;
// The following code initializes the Global Set Reset (GSR) and Global Three-State (GTS) nets
// Refer to the Synthesis and Simulation Design Guide for more information on this process
reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GSR = 1;
GTS = 0; // GTS is not activated by default
#100; // GSR is set for 100 ns
GSR = 0;
end
// Initialize Inputs
`ifdef auto_init
initial begin
end
`endif
endmodule
这是WARING和ERROR
WARNING: could not create F:/FPGA store/ISE/one4two/test_one4two1.v. Defaulting to boilerplate.
ERROR:Portability:90 - Command line error: Unexpected argumentUsage: vhdtdtfi {-lib <libname> {<vhdfile>}} [-lang vhdl|verilog] [-module
求高人解答！！我的QQ是904122918，如能在线帮忙，感激不尽~~
页:
[1]
